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k60p144m120sf3 k60 sub-family data sheet supports the following: mk60fx512vlq12, mk60fn1m0vlq12, MK60FX512VMD12, mk60fn1m0vmd12 features ? operating characteristics C voltage range: 1.71 to 3.6 v C flash write voltage range: 1.71 to 3.6 v C temperature range (ambient): -40 to 105c ? performance C up to 120 mhz arm cortex-m4 core with dsp instructions delivering 1.25 dhrystone mips per mhz ? memories and memory interfaces C up to 1024 kb program flash memory on non- flexmemory devices C up to 512 kb program flash memory on flexmemory devices C up to 512 kb flexnvm on flexmemory devices C 16 kb flexram on flexmemory devices C up to 128 kb ram C serial programming interface (ezport) C flexbus external bus interface C nand flash controller interface ? clocks C 3 to 32 mhz crystal oscillator C 32 khz crystal oscillator C multi-purpose clock generator ? system peripherals C 10 low-power modes to provide power optimization based on application requirements C memory protection unit with multi-master protection C 32-channel dma controller, supporting up to 128 request sources C external watchdog monitor C software watchdog C low-leakage wakeup unit ? security and integrity modules C hardware crc module to support fast cyclic redundancy checks C hardware random-number generator C hardware encryption supporting des, 3des, aes, md5, sha-1, and sha-256 algorithms C 128-bit unique identification (id) number per chip ? human-machine interface C low-power hardware touch sensor interface (tsi) C general-purpose input/output ? analog modules C four 16-bit sar adcs C programmable gain amplifier (pga) (up to x64) integrated into each adc C two 12-bit dacs C four analog comparators (cmp) containing a 6-bit dac and programmable reference input C voltage reference ? timers C programmable delay block C two 8-channel motor control/general purpose/pwm timers C two 2-channel quadrature decoder/general purpose timers C ieee 1588 timers C periodic interrupt timers C 16-bit low-power timer C carrier modulator transmitter C real-time clock freescale semiconductor document number: k60p144m120sf3 data sheet: advance information rev. 3, 2/2012 this document contains information on a new product. specifications and information herein are subject to change without notice. ? 2012 freescale semiconductor, inc. preliminary
? communication interfaces C ethernet controller with mii and rmii interface to external phy and hardware ieee 1588 capability C usb high-/full-/low-speed on-the-go controller with ulpi interface C usb full-/low-speed on-the-go controller with on-chip transceiver C two controller area network (can) modules C three spi modules C two i2c modules C six uart modules C secure digital host controller (sdhc) C two i2s modules k60 sub-family data sheet data sheet, rev. 3, 2/2012. 2 preliminary freescale semiconductor, inc.
table of contents 1 ordering parts ........................................................................... 5 1.1 determining valid orderable parts...................................... 5 2 part identification ...................................................................... 5 2.1 description......................................................................... 5 2.2 format ............................................................................... 5 2.3 fields ................................................................................. 5 2.4 example ............................................................................ 6 3 terminology and guidelines ...................................................... 6 3.1 definition: operating requirement...................................... 6 3.2 definition: operating behavior ........................................... 6 3.3 definition: attribute ............................................................ 7 3.4 definition: rating ............................................................... 7 3.5 result of exceeding a rating .............................................. 8 3.6 relationship between ratings and operating requirements...................................................................... 8 3.7 guidelines for ratings and operating requirements............ 8 3.8 definition: typical value..................................................... 9 3.9 typical value conditions .................................................... 10 4 ratings ...................................................................................... 10 4.1 thermal handling ratings ................................................... 10 4.2 moisture handling ratings .................................................. 11 4.3 esd handling ratings ......................................................... 11 4.4 voltage and current operating ratings ............................... 11 5 general ..................................................................................... 12 5.1 ac electrical characteristics .............................................. 12 5.2 nonswitching electrical specifications ............................... 12 5.2.1 voltage and current operating requirements ...... 12 5.2.2 lvd and por operating requirements ............... 13 5.2.3 voltage and current operating behaviors ............ 14 5.2.4 power mode transition operating behaviors ....... 15 5.2.5 power consumption operating behaviors............ 16 5.2.6 emc radiated emissions operating behaviors .... 20 5.2.7 designing with radiated emissions in mind ......... 21 5.2.8 capacitance attributes ........................................ 21 5.3 switching specifications..................................................... 21 5.3.1 device clock specifications ................................. 21 5.3.2 general switching specifications......................... 22 5.4 thermal specifications ....................................................... 23 5.4.1 thermal operating requirements......................... 23 5.4.2 thermal attributes ............................................... 23 6 peripheral operating requirements and behaviors .................... 24 6.1 core modules .................................................................... 24 6.1.1 debug trace timing specifications ....................... 24 6.1.2 jtag electricals.................................................. 25 6.2 system modules ................................................................ 28 6.3 clock modules ................................................................... 28 6.3.1 mcg specifications ............................................. 28 6.3.2 oscillator electrical specifications ....................... 30 6.3.3 32khz oscillator electrical characteristics ......... 32 6.4 memories and memory interfaces ..................................... 33 6.4.1 flash (ftfe) electrical specifications ................. 33 6.4.2 ezport switching specifications ......................... 36 6.4.3 nfc specifications .............................................. 37 6.4.4 flexbus switching specifications........................ 40 6.5 security and integrity modules .......................................... 43 6.6 analog ............................................................................... 43 6.6.1 adc electrical specifications .............................. 43 6.6.2 cmp and 6-bit dac electrical specifications ...... 52 6.6.3 12-bit dac electrical characteristics ................... 54 6.6.4 voltage reference electrical specifications.......... 57 6.7 timers................................................................................ 58 6.8 communication interfaces ................................................. 58 6.8.1 ethernet switching specifications ........................ 58 6.8.2 usb electrical specifications............................... 60 6.8.3 usb dcd electrical specifications ...................... 60 6.8.4 usb vreg electrical specifications ................... 61 6.8.5 ulpi timing specifications................................... 61 6.8.6 can switching specifications .............................. 62 6.8.7 dspi switching specifications (limited voltage range) ................................................................. 63 6.8.8 dspi switching specifications (full voltage range) ................................................................. 64 6.8.9 i2c switching specifications ................................ 66 6.8.10 uart switching specifications............................ 66 6.8.11 sdhc specifications ........................................... 66 6.8.12 i2s/sai switching specifications ........................ 67 6.9 human-machine interfaces (hmi)...................................... 69 6.9.1 tsi electrical specifications ................................ 69 k60 sub-family data sheet data sheet, rev. 3, 2/2012. freescale semiconductor, inc. preliminary 3
7 dimensions ............................................................................... 70 7.1 obtaining package dimensions ......................................... 71 8 pinout ........................................................................................ 71 8.1 k60 signal multiplexing and pin assignments .................. 71 8.2 k60 pinouts ....................................................................... 78 9 revision history ........................................................................ 80 k60 sub-family data sheet data sheet, rev. 3, 2/2012. 4 preliminary freescale semiconductor, inc.
1 ordering parts 1.1 determining valid orderable parts valid orderable part numbers are provided on the web. to determine the orderable part numbers for this device, go to http://www.freescale.com and perform a part number search for the following device numbers: pk60 and mk60. 2 part identification 2.1 description part numbers for the chip have fields that identify the specific part. you can use the values of these fields to determine the specific part you have received. 2.2 format part numbers for this device have the following format: q k## a m fff t pp cc n 2.3 fields this table lists the possible values for each field in the part number (not all combinations are valid): field description values q qualification status ? m = fully qualified, general market flow ? p = prequalification k## kinetis family ? k60 a key attribute ? d = cortex-m4 w/ dsp ? f = cortex-m4 w/ dsp and fpu m flash memory type ? n = program flash only ? x = program flash and flexmemory table continues on the next page... ordering parts k60 sub-family data sheet data sheet, rev. 3, 2/2012. freescale semiconductor, inc. preliminary 5
field description values fff program flash memory size ? 32 = 32 kb ? 64 = 64 kb ? 128 = 128 kb ? 256 = 256 kb ? 512 = 512 kb ? 1m0 = 1 mb t temperature range (c) ? v = C40 to 105 ? c = C40 to 85 pp package identifier ? lq = 144 lqfp (20 mm x 20 mm) ? md = 144 mapbga (13 mm x 13 mm) cc maximum cpu frequency (mhz) ? 12 = 120 mhz n packaging type ? r = tape and reel ? (blank) = trays 2.4 example this is an example part number: mk60fn1m0vlq12 3 terminology and guidelines 3.1 definition: operating requirement an operating requirement is a specified value or range of values for a technical characteristic that you must guarantee during operation to avoid incorrect operation and possibly decreasing the useful life of the chip. 3.1.1 example this is an example of an operating requirement, which you must meet for the accompanying operating behaviors to be guaranteed: symbol description min. max. unit v dd 1.0 v core supply voltage 0.9 1.1 v terminology and guidelines k60 sub-family data sheet data sheet, rev. 3, 2/2012. 6 preliminary freescale semiconductor, inc.
3.2 definition: operating behavior an operating behavior is a specified value or range of values for a technical characteristic that are guaranteed during operation if you meet the operating requirements and any other specified conditions. 3.2.1 example this is an example of an operating behavior, which is guaranteed if you meet the accompanying operating requirements: symbol description min. max. unit i wp digital i/o weak pullup/ pulldown current 10 130 a 3.3 definition: attribute an attribute is a specified value or range of values for a technical characteristic that are guaranteed, regardless of whether you meet the operating requirements. 3.3.1 example this is an example of an attribute: symbol description min. max. unit cin_d input capacitance: digital pins 7 pf 3.4 definition: rating a rating is a minimum or maximum value of a technical characteristic that, if exceeded, may cause permanent chip failure: ? operating ratings apply during operation of the chip. ? handling ratings apply when the chip is not powered. terminology and guidelines k60 sub-family data sheet data sheet, rev. 3, 2/2012. freescale semiconductor, inc. preliminary 7
3.4.1 example this is an example of an operating rating: symbol description min. max. unit v dd 1.0 v core supply voltage C0.3 1.2 v 3.5 result of exceeding a rating 40 30 20 10 0 measured characteristic operating rating failures in time (ppm) the likelihood of permanent chip failure increases rapidly as soon as a characteristic begins to exceed one of its operating ratings. 3.6 relationship between ratings and operating requirements C - no permanent failure - correct operation normal operating range limited operating range - no permanent failure - possible decreased life - possible incorrect operation fatal range - probable permanent failure limited operating range - no permanent failure - possible decreased life - possible incorrect operation handling range - no permanent failure fatal range - probable permanent failure operating or handling rating (max.) operating requirement (max.) operating requirement (min.) operating or handling rating (min.) 3.7 guidelines for ratings and operating requirements follow these guidelines for ratings and operating requirements: ? never exceed any of the chips ratings. terminology and guidelines k60 sub-family data sheet data sheet, rev. 3, 2/2012. 8 preliminary freescale semiconductor, inc.
? during normal operation, dont exceed any of the chips operating requirements. ? if you must exceed an operating requirement at times other than during normal operation (for example, during power sequencing), limit the duration as much as possible. 3.8 definition: typical value a typical value is a specified value for a technical characteristic that: ? lies within the range of values specified by the operating behavior ? given the typical manufacturing process, is representative of that characteristic during operation when you meet the typical-value conditions or other specified conditions typical values are provided as design guidelines and are neither tested nor guaranteed. 3.8.1 example 1 this is an example of an operating behavior that includes a typical value: symbol description min. typ. max. unit i wp digital i/o weak pullup/pulldown current 10 70 130 a 3.8.2 example 2 this is an example of a chart that shows typical values for various voltage and temperature conditions: terminology and guidelines k60 sub-family data sheet data sheet, rev. 3, 2/2012. freescale semiconductor, inc. preliminary 9
0.90 0.95 1.00 1.05 1.10 0 500 1000 1500 2000 2500 3000 3500 4000 4500 5000 150 c 105 c 25 c C40 c v dd (v) i (a) dd_stop t j 3.9 typical value conditions typical values assume you meet the following conditions (or other conditions as specified): symbol description value unit t a ambient temperature 25 c v dd 3.3 v supply voltage 3.3 v 4 ratings 4.1 thermal handling ratings symbol description min. max. unit notes t stg storage temperature C55 150 c 1 t sdr solder temperature, lead-free 260 c 2 1. determined according to jedec standard jesd22-a103, high temperature storage life . 2. determined according to ipc/jedec standard j-std-020, moisture/reflow sensitivity classification for nonhermetic solid state surface mount devices . ratings k60 sub-family data sheet data sheet, rev. 3, 2/2012. 10 preliminary freescale semiconductor, inc.
4.2 moisture handling ratings symbol description min. max. unit notes msl moisture sensitivity level 3 1 1. determined according to ipc/jedec standard j-std-020, moisture/reflow sensitivity classification for nonhermetic solid state surface mount devices . 4.3 esd handling ratings symbol description min. max. unit notes v hbm electrostatic discharge voltage, human body model -2000 +2000 v 1 v cdm electrostatic discharge voltage, charged-device model -500 +500 v 2 i lat latch-up current at ambient temperature of 105c -100 +100 ma 1. determined according to jedec standard jesd22-a114, electrostatic discharge (esd) sensitivity testing human body model (hbm) . 2. determined according to jedec standard jesd22-c101, field-induced charged-device model test method for electrostatic-discharge-withstand thresholds of microelectronic components . 4.4 voltage and current operating ratings symbol description min. max. unit v dd digital supply voltage 1 C0.3 3.8 v i dd digital supply current 300 ma v dio digital input voltage (except reset, extal0/xtal0, and extal1/xtal1) 2 C0.3 5.5 v v aio analog 3 , reset, extal0/xtal0, and extal1/xtal1 input voltage C0.3 v dd + 0.3 v i d instantaneous maximum current single pin limit (applies to all digital pins except pins) C25 25 ma v dda analog supply voltage v dd C 0.3 v dd + 0.3 v v usb_dp usb_dp input voltage C0.3 3.63 v v usb_dm usb_dm input voltage C0.3 3.63 v vregin usb regulator input C0.3 6.0 v v bat rtc battery supply voltage C0.3 3.8 v 1. it applies for all port pins. 2. it covers digital pins. 3. analog pins are defined as pins that do not have an associated general purpose i/o port function. ratings k60 sub-family data sheet data sheet, rev. 3, 2/2012. freescale semiconductor, inc. preliminary 11
5 general 5.1 ac electrical characteristics unless otherwise specified, propagation delays are measured from the 50% to the 50% point, and rise and fall times are measured at the 20% and 80% points, as shown in the following figure. figure 1. input signal measurement reference all digital i/o switching characteristics assume: 1. output pins ? have c l =30pf loads, ? are configured for fast slew rate (portx_pcrn[sre]=0), and ? are configured for high drive strength (portx_pcrn[dse]=1) 2. input pins ? have their passive filter disabled (portx_pcrn[pfe]=0) 5.2 nonswitching electrical specifications 5.2.1 voltage and current operating requirements table 1. voltage and current operating requirements symbol description min. max. unit notes v dd supply voltage 1.71 3.6 v v dda analog supply voltage 1.71 3.6 v v dd C v dda v dd -to-v dda differential voltage C0.1 0.1 v v ss C v ssa v ss -to-v ssa differential voltage C0.1 0.1 v v bat rtc battery supply voltage 1.71 3.6 v table continues on the next page... general k60 sub-family data sheet data sheet, rev. 3, 2/2012. 12 preliminary freescale semiconductor, inc.
table 1. voltage and current operating requirements (continued) symbol description min. max. unit notes v ih input high voltage (digital pins) ? 2.7 v v dd 3.6 v ? 1.7 v v dd 2.7 v 0.7 v dd 0.75 v dd v v v il input low voltage (digital pins) ? 2.7 v v dd 3.6 v ? 1.7 v v dd 2.7 v 0.35 v dd 0.3 v dd v v v hys input hysteresis (digital pins) 0.06 v dd v i icdio digital pin negative dc injection current single pin ? v in < v ss -0.3v -5 ma 1 i icaio analog 2 , extal0/xtal0, and extal1/xtal1 pin dc injection current single pin ? v in < v ss -0.3v (negative current injection) ? v in > v dd +0.3v (positive current injection) -5 +5 ma 3 i iccont contiguous pin dc injection current regional limit, includes sum of negative injection currents or sum of positive injection currents of 16 contiguous pins ? negative current injection ? positive current injection -25 +25 ma v ram v dd voltage required to retain ram 1.2 v v rfvbat v bat voltage required to retain the vbat register file v por_vbat v 1. all 5 v tolerant digital i/o pins are internally clamped to v ss through a esd protection diode. there is no diode connection to v dd . if v in greater than v dio_min (=v ss -0.3v) is observed, then there is no need to provide current limiting resistors at the pads. if this limit cannot be observed then a current limiting resistor is required. the negative dc injection current limiting resistor is calculated as r=(v dio_min -v in )/|i ic |. 2. analog pins are defined as pins that do not have an associated general purpose i/o port function. 3. all analog pins are internally clamped to v ss and v dd through esd protection diodes. if v in is greater than v aio_min (=v ss -0.3v) and v in is less than v aio_max (=v dd +0.3v) is observed, then there is no need to provide current limiting resistors at the pads. if these limits cannot be observed then a current limiting resistor is required. the negative dc injection current limiting resistor is calculated as r=(v aio_min -v in )/|i ic |. the positive injection current limiting resistor is calcualted as r=(v in -v aio_max )/|i ic |. select the larger of these two calculated resistances. 5.2.2 lvd and por operating requirements table 2. lvd and por operating requirements symbol description min. typ. max. unit notes v por falling vdd por detect voltage 0.8 1.1 1.5 v table continues on the next page... general k60 sub-family data sheet data sheet, rev. 3, 2/2012. freescale semiconductor, inc. preliminary 13
table 2. lvd and por operating requirements (continued) symbol description min. typ. max. unit notes v lvdh falling low-voltage detect threshold high range (lvdv=01) 2.48 2.56 2.64 v v lvw1h v lvw2h v lvw3h v lvw4h low-voltage warning thresholds high range ? level 1 falling (lvwv=00) ? level 2 falling (lvwv=01) ? level 3 falling (lvwv=10) ? level 4 falling (lvwv=11) 2.62 2.72 2.82 2.92 2.70 2.80 2.90 3.00 2.78 2.88 2.98 3.08 v v v v 1 v hysh low-voltage inhibit reset/recover hysteresis high range 80 mv v lvdl falling low-voltage detect threshold low range (lvdv=00) 1.54 1.60 1.66 v v lvw1l v lvw2l v lvw3l v lvw4l low-voltage warning thresholds low range ? level 1 falling (lvwv=00) ? level 2 falling (lvwv=01) ? level 3 falling (lvwv=10) ? level 4 falling (lvwv=11) 1.74 1.84 1.94 2.04 1.80 1.90 2.00 2.10 1.86 1.96 2.06 2.16 v v v v 1 v hysl low-voltage inhibit reset/recover hysteresis low range 60 mv v bg bandgap voltage reference 0.97 1.00 1.03 v t lpo internal low power oscillator period factory trimmed 900 1000 1100 s 1. rising thresholds are falling threshold + hysteresis voltage table 3. vbat power operating requirements symbol description min. typ. max. unit notes v por_vbat falling vbat supply por detect voltage 0.8 1.1 1.5 v general k60 sub-family data sheet data sheet, rev. 3, 2/2012. 14 preliminary freescale semiconductor, inc.
5.2.3 voltage and current operating behaviors table 4. voltage and current operating behaviors symbol description min. max. unit notes v oh output high voltage high drive strength ? 2.7 v v dd 3.6 v, i oh = -9ma ? 1.71 v v dd 2.7 v, i oh = -3ma v dd C 0.5 v dd C 0.5 v v output high voltage low drive strength ? 2.7 v v dd 3.6 v, i oh = -2ma ? 1.71 v v dd 2.7 v, i oh = -0.6ma v dd C 0.5 v dd C 0.5 v v i oht output high current total for all ports 100 ma i oht_io60 output high current total for fast digital ports 100 ma v ol output low voltage high drive strength ? 2.7 v v dd 3.6 v, i ol = 9ma ? 1.71 v v dd 2.7 v, i ol = 3ma 0.5 0.5 v v output low voltage low drive strength ? 2.7 v v dd 3.6 v, i ol = 2ma ? 1.71 v v dd 2.7 v, i ol = 0.6ma 0.5 0.5 v v i olt output low current total for all ports tbd ma i olt_io60 output low current total for fast digital ports tbd ma i in input leakage current (per pin) for full temperature range 1 a 1 i in input leakage current (per pin) at 25c 0.025 a 1 i oz hi-z (off-state) leakage current (per pin) 1 a r pu internal pullup resistors 20 50 k 2 r pd internal pulldown resistors 20 50 k 3 1. measured at vdd=3.6v 2. measured at v dd supply voltage = v dd min and vinput = v ss 3. measured at v dd supply voltage = v dd min and vinput = v dd 5.2.4 power mode transition operating behaviors all specifications except t por , and vllsx run recovery times in the following table assume this clock configuration: ? cpu and system clocks = fei 100 mhz ? bus clock = 50 mhz general k60 sub-family data sheet data sheet, rev. 3, 2/2012. freescale semiconductor, inc. preliminary 15
? flexbus clock = 50 mhz ? flash clock = 25 mhz table 5. power mode transition operating behaviors symbol description min. max. unit notes t por after a por event, amount of time from the point v dd reaches 1.71 v to execution of the first instruction across the operating temperature range of the chip. 300 s 1 ? vlls1 run 126 s ? vlls2 run 82 s ? vlls3 run 82 s ? lls run 5.0 s ? vlps run tbd s ? stop run tbd s 1. normal boot (ftfe_fopt[lpboot]=1) 5.2.5 power consumption operating behaviors table 6. power consumption operating behaviors symbol description min. typ. max. unit notes i dda analog supply current see note ma 1 i dd_run run mode current all peripheral clocks disabled, code executing from flash ? @ 1.8v ? @ 3.0v 65 65 tbd tbd ma ma 2 i dd_run run mode current all peripheral clocks enabled, code executing from flash ? @ 1.8v ? @ 3.0v 95 95 tbd tbd ma ma 3 i dd_wait wait mode high frequency current at 3.0 v all peripheral clocks disabled 37 tbd ma 2 i dd_wait wait mode reduced frequency current at 3.0 v all peripheral clocks disabled 21 tbd ma 4 table continues on the next page... general k60 sub-family data sheet data sheet, rev. 3, 2/2012. 16 preliminary freescale semiconductor, inc.
table 6. power consumption operating behaviors (continued) symbol description min. typ. max. unit notes i dd_stop stop mode current at 3.0 v ? @ C40 to 25c ? @ 70c ? @ 105c tbd tbd tbd tbd tbd tbd ma ma ma i dd_vlpr very-low-power run mode current at 3.0 v all peripheral clocks disabled 2.3 tbd ma 5 i dd_vlpr very-low-power run mode current at 3.0 v all peripheral clocks enabled 3.1 tbd ma 6 i dd_vlpw very-low-power wait mode current at 3.0 v 1.8 tbd ma 7 i dd_vlps very-low-power stop mode current at 3.0 v ? @ C40 to 25c ? @ 70c ? @ 105c 200 tbd tbd tbd tbd tbd a a a i dd_lls low leakage stop mode current at 3.0 v ? @ C40 to 25c ? @ 70c ? @ 105c 200 tbd tbd tbd tbd tbd a a a 8 i dd_vlls3 very low-leakage stop mode 3 current at 3.0 v ? @ C40 to 25c ? @ 70c ? @ 105c 6.5 37.4 148.3 tbd tbd tbd a a a #new- reference/ llsramn i dd_vlls2 very low-leakage stop mode 2 current at 3.0 v ? @ C40 to 25c ? @ 70c ? @ 105c 3.4 13.4 58.5 tbd tbd tbd a a a i dd_vlls1 very low-leakage stop mode 1 current at 3.0 v ? @ C40 to 25c ? @ 70c ? @ 105c 2.9 9.8 44.7 tbd tbd tbd a a a i dd_vbat average current when cpu is not accessing rtc registers at 3.0 v ? @ C40 to 25c ? @ 70c ? @ 105c 0.91 1.5 4.3 1.1 1.85 4.3 a a a 9 1. the analog supply current is the sum of the active or disabled current for each of the analog modules on the device. see each module's specification for its supply current. general k60 sub-family data sheet data sheet, rev. 3, 2/2012. freescale semiconductor, inc. preliminary 17
2. 120 mhz core and system clock, 60 mhz bus, 30 mhz flexbus clock, and 20 mhz flash clock. mcg configured for pee mode. all peripheral clocks disabled. 3. 120 mhz core and system clock, 60 mhz bus, 50 mhz flexbus clock, and 20 mhz flash clock. mcg configured for pee mode. all peripheral clocks enabled, but peripherals are not in active operation. 4. 25 mhz core and system clock, 25 mhz bus clock, and 12.5 mhz flexbus and flash clock. mcg configured for fei mode. 5. 4 mhz core, system, 2 mhz flexbus, and 2 mhz bus clock and 1 mhz flash clock. mcg configured for blpe mode. all peripheral clocks disabled. 6. 4 mhz core, system, 2 mhz flexbus, and 2 mhz bus clock and 1 mhz flash clock. mcg configured for blpe mode. all peripheral clocks disabled. 7. 4 mhz core, system, 2 mhz flexbus, and 2 mhz bus clock and 1 mhz flash clock. mcg configured for blpe mode. all peripheral clocks disabled. 8. data reflects devices with 128 kb of ram. for devices with 64 kb of ram, power consumption is reduced by 2 a. 9. includes 32khz oscillator current and rtc operation. 5.2.5.1 diagram: typical idd_run operating behavior the following data was measured under these conditions: ? mcg in fbe mode for 50 mhz and lower frequencies. mcg in fee mode at greater than 50 mhz frequencies. mcg in pee mode is greater than 100 mhz frequencies. ? usb regulator disabled ? no gpios toggled ? code execution from flash with cache enabled ? for the alloff curve, all peripheral clocks are disabled except ftfl general k60 sub-family data sheet data sheet, rev. 3, 2/2012. 18 preliminary freescale semiconductor, inc.
figure 2. run mode supply current vs. core frequency general k60 sub-family data sheet data sheet, rev. 3, 2/2012. freescale semiconductor, inc. preliminary 19
figure 3. vlpr mode supply current vs. core frequency 5.2.6 emc radiated emissions operating behaviors table 7. emc radiated emissions operating behaviors for 256mapbga symbol description frequency band (mhz) typ. unit notes v re1 radiated emissions voltage, band 1 0.15C50 tbd dbv 1 , 2 v re2 radiated emissions voltage, band 2 50C150 tbd dbv v re3 radiated emissions voltage, band 3 150C500 tbd dbv v re4 radiated emissions voltage, band 4 500C1000 tbd dbv v re_iec iec level 0.15C1000 k 2 , 3 1. determined according to iec standard 61967-1, integrated circuits - measurement of electromagnetic emissions, 150 khz to 1 ghz part 1: general conditions and definitions and iec standard 61967-2, integrated circuits - measurement of electromagnetic emissions, 150 khz to 1 ghz part 2: measurement of radiated emissionstem cell and wideband tem cell method . measurements were made while the microcontroller was running basic application code. the reported emission level is the value of the maximum measured emission, rounded up to the next whole number, from among the measured orientations in each frequency range. 2. v dd = 3.3 v, t a = 25 c, f osc = 12 mhz (crystal), f sys = 96 mhz, f bus = 48 mhz general k60 sub-family data sheet data sheet, rev. 3, 2/2012. 20 preliminary freescale semiconductor, inc.
3. specified according to annex d of iec standard 61967-2, measurement of radiated emissionstem cell and wideband tem cell method 5.2.7 designing with radiated emissions in mind to find application notes that provide guidance on designing your system to minimize interference from radiated emissions: 1. go to http://www.freescale.com . 2. perform a keyword search for emc design. 5.2.8 capacitance attributes table 8. capacitance attributes symbol description min. max. unit c in_a input capacitance: analog pins 7 pf c in_d input capacitance: digital pins 7 pf c in_d_io60 input capacitance: fast digital pins 9 pf 5.3 switching specifications 5.3.1 device clock specifications table 9. device clock specifications symbol description min. max. unit notes normal run mode f sys system and core clock 120 mhz f sys_usbfs system and core clock when full speed usb in operation 20 mhz f sys_usbhs system and core clock when high speed usb in operation 60 mhz f enet system and core clock when ethernet in operation ? 10 mbps ? 100 mbps 5 50 mhz f bus bus clock 60 mhz fb_clk flexbus clock 50 mhz f flash flash clock 25 mhz table continues on the next page... general k60 sub-family data sheet data sheet, rev. 3, 2/2012. freescale semiconductor, inc. preliminary 21
table 9. device clock specifications (continued) symbol description min. max. unit notes f lptmr lptmr clock 25 mhz vlpr mode 1 f sys system and core clock 4 mhz f bus bus clock 4 mhz fb_clk flexbus clock 4 mhz f flash flash clock 1 mhz f lptmr lptmr clock 4 mhz 1. the frequency limitations in vlpr mode here override any frequency specification listed in the timing specification for any other module. 5.3.2 general switching specifications these general purpose specifications apply to all signals configured for gpio, uart, can, cmt, ieee 1588 timer, and i 2 c signals. table 10. general switching specifications symbol description min. max. unit notes gpio pin interrupt pulse width (digital glitch filter disabled) synchronous path 1.5 bus clock cycles 1 gpio pin interrupt pulse width (digital glitch filter disabled, analog filter enabled) asynchronous path 100 ns 2 gpio pin interrupt pulse width (digital glitch filter disabled, analog filter disabled) asynchronous path 16 ns 2 external reset pulse width (digital glitch filter disabled) 100 ns 2 mode select ( ezp_cs) hold time after reset deassertion 2 bus clock cycles t io50 port rise and fall time (high drive strength) ? slew disabled ? slew enabled tbd tbd ns ns 3 4 t io50 port rise and fall time (low drive strength) ? slew disabled ? slew enabled tbd tbd ns ns 3 4 t io60 port rise and fall time (high drive strength) ? slew disabled ? slew enabled tbd tbd ns ns 3 4 table continues on the next page... general k60 sub-family data sheet data sheet, rev. 3, 2/2012. 22 preliminary freescale semiconductor, inc.
table 10. general switching specifications (continued) symbol description min. max. unit notes t io60 port rise and fall time (low drive strength) ? slew disabled ? slew enabled tbd tbd ns ns 3 4 t tamper port rise and fall time (high drive strength) ? slew disabled ? slew enabled tbd tbd ns ns 5 6 t tamper port rise and fall time (low drive strength) ? slew disabled ? slew enabled tbd tbd ns ns 7 8 1. the greater synchronous and asynchronous timing must be met. 2. this is the shortest pulse that is guaranteed to be recognized. 3. 25pf load 4. 15pf load 5. 75pf load 6. 15pf load 7. 75pf load 8. 15pf load 5.4 thermal specifications 5.4.1 thermal operating requirements table 11. thermal operating requirements symbol description min. max. unit t j die junction temperature C40 125 c t a ambient temperature C40 105 c 5.4.2 thermal attributes board type symbol description 144 lqfp 144 mapbga unit notes single-layer (1s) r ja thermal resistance, junction to ambient (natural convection) 45 50 c/w 1 table continues on the next page... general k60 sub-family data sheet data sheet, rev. 3, 2/2012. freescale semiconductor, inc. preliminary 23
board type symbol description 144 lqfp 144 mapbga unit notes four-layer (2s2p) r ja thermal resistance, junction to ambient (natural convection) 36 30 c/w 1 single-layer (1s) r jma thermal resistance, junction to ambient (200 ft./ min. air speed) 36 41 c/w 1 four-layer (2s2p) r jma thermal resistance, junction to ambient (200 ft./ min. air speed) 30 27 c/w 1 r jb thermal resistance, junction to board 24 17 c/w 2 r jc thermal resistance, junction to case 9 10 c/w 3 jt thermal characterization parameter, junction to package top outside center (natural convection) 2 2 c/w 4 1. determined according to jedec standard jesd51-2, integrated circuits thermal test method environmental conditionsnatural convection (still air) , or eia/jedec standard jesd51-6, integrated circuit thermal test method environmental conditionsforced convection (moving air) . 2. determined according to jedec standard jesd51-8, integrated circuit thermal test method environmental conditionsjunction-to-board . 3. determined according to method 1012.1 of mil-std 883, test method standard, microcircuits , with the cold plate temperature used for the case temperature. the value includes the thermal resistance of the interface material between the top of the package and the cold plate. 4. determined according to jedec standard jesd51-2, integrated circuits thermal test method environmental conditionsnatural convection (still air) . 6 peripheral operating requirements and behaviors 6.1 core modules peripheral operating requirements and behaviors k60 sub-family data sheet data sheet, rev. 3, 2/2012. 24 preliminary freescale semiconductor, inc.
6.1.1 debug trace timing specifications table 12. debug trace operating behaviors symbol description min. max. unit t cyc clock period frequency dependent mhz t wl low pulse width 2 ns t wh high pulse width 2 ns t r clock and data rise time 3 ns t f clock and data fall time 3 ns t s data setup 3 ns t h data hold 2 ns figure 4. trace_clkout specifications th ts ts th trace_clkout trace_d[3:0] figure 5. trace data specifications 6.1.2 jtag electricals table 13. jtag voltage range electricals symbol description min. max. unit operating voltage 2.7 5.5 v j1 tclk frequency of operation ? jtag ? cjtag 10 5 mhz j2 tclk cycle period 1/j1 ns table continues on the next page... peripheral operating requirements and behaviors k60 sub-family data sheet data sheet, rev. 3, 2/2012. freescale semiconductor, inc. preliminary 25
table 13. jtag voltage range electricals (continued) symbol description min. max. unit j3 tclk clock pulse width ? jtag ? cjtag 100 200 ns ns ns j4 tclk rise and fall times 1 ns j5 tms input data setup time to tclk rise ? jtag ? cjtag 53 112 ns j6 tdi input data setup time to tclk rise 8 ns j7 tms input data hold time after tclk rise ? jtag ? cjtag 3.4 3.4 ns j8 tdi input data hold time after tclk rise 3.4 ns j9 tclk low to tms data valid ? jtag ? cjtag 48 85 ns j10 tclk low to tdo data valid 48 ns j11 output data hold/invalid time after clock edge 1 3 ns 1. they are common for jtag and cjtag. j2 j3 j3 j4 j4 tclk (input) figure 6. test clock input timing peripheral operating requirements and behaviors k60 sub-family data sheet data sheet, rev. 3, 2/2012. 26 preliminary freescale semiconductor, inc.
j7 j8 j7 j5 j6 input data valid output data valid output data valid tclk data inputs data outputs data outputs data outputs figure 7. boundary scan (jtag) timing j11 j12 j11 j9 j10 input data valid output data valid output data valid tclk tdi/tms tdo tdo tdo figure 8. test access port timing peripheral operating requirements and behaviors k60 sub-family data sheet data sheet, rev. 3, 2/2012. freescale semiconductor, inc. preliminary 27
j14 j13 tclk trst figure 9. trst timing 6.2 system modules there are no specifications necessary for the device's system modules. 6.3 clock modules 6.3.1 mcg specifications table 14. mcg specifications symbol description min. typ. max. unit notes f ints_ft internal reference frequency (slow clock) factory trimmed at nominal vdd and 25 c 32.768 khz f ints_t internal reference frequency (slow clock) user trimmed 31.25 39.0625 khz i ints internal reference (slow clock) current tbd a fdco_res_t resolution of trimmed average dco output frequency at fixed voltage and temperature using sctrim and scftrim 0.3 0.6 %f dco 1 f dco_res_t resolution of trimmed average dco output frequency at fixed voltage and temperature using sctrim only 0.2 0.5 %f dco 1 f dco_t total deviation of trimmed average dco output frequency over voltage and temperature 10 %f dco 1 f dco_t total deviation of trimmed average dco output frequency over fixed voltage and temperature range of 0C70c 4.5 %f dco 1 f intf_ft internal reference frequency (fast clock) factory trimmed at nominal vdd and 25c 4 mhz f intf_t internal reference frequency (fast clock) user trimmed at nominal vdd and 25 c 3 5 mhz i intf internal reference (fast clock) current tbd a table continues on the next page... peripheral operating requirements and behaviors k60 sub-family data sheet data sheet, rev. 3, 2/2012. 28 preliminary freescale semiconductor, inc.
table 14. mcg specifications (continued) symbol description min. typ. max. unit notes f loc_low loss of external clock minimum frequency range = 00 (3/5) x f ints_t khz f loc_high loss of external clock minimum frequency range = 01, 10, or 11 (16/5) x f ints_t khz fll f fll_ref fll reference frequency range 31.25 39.0625 khz f dco dco output frequency range low range (drs=00) 640 f fll_ref 20 20.97 25 mhz 2 , 3 mid range (drs=01) 1280 f fll_ref 40 41.94 50 mhz mid-high range (drs=10) 1920 f fll_ref 60 62.91 75 mhz high range (drs=11) 2560 f fll_ref 80 83.89 100 mhz f dco_t_dmx3 2 dco output frequency low range (drs=00) 732 f fll_ref 23.99 mhz 4 , 5 mid range (drs=01) 1464 f fll_ref 47.97 mhz mid-high range (drs=10) 2197 f fll_ref 71.99 mhz high range (drs=11) 2929 f fll_ref 95.98 mhz j cyc_fll fll period jitter ? f vco = 48 mhz ? f vco = 98 mhz 180 150 ps j acc_fll fll accumulated jitter of dco output over a 1s time window tbd ps t fll_acquire fll target frequency acquisition time 1 ms 6 pll0,1 f pll_ref pll reference frequency range 8 16 mhz f vcoclk_2x vco output frequency 180 360 mhz f vcoclk pll output frequency 90 180 mhz f vcoclk_90 pll quadrature output frequency 90 180 mhz i pll pll operating current (fast) tbd a 7 table continues on the next page... peripheral operating requirements and behaviors k60 sub-family data sheet data sheet, rev. 3, 2/2012. freescale semiconductor, inc. preliminary 29
table 14. mcg specifications (continued) symbol description min. typ. max. unit notes i pll pll operating current (fast) tbd a 7 t pll_lock lock detector detection time 100 10 -6 + 1075(1/ f pll_ref ) s 8 j cyc_pll jitter (cycle to cycle) 50 tbd ps j acc_pll jitter (accumulated) 500 tbd ps 9 1. this parameter is measured with the internal reference (slow clock) being used as a reference to the fll (fei clock mode). 2. these typical values listed are with the slow internal reference clock (fei) using factory trim and dmx32=0. 3. the resulting system clock frequencies should not exceed their maximum specified values. the dco frequency deviation ( f dco_t ) over voltage and temperature should be considered. 4. these typical values listed are with the slow internal reference clock (fei) using factory trim and dmx32=1. 5. the resulting clock frequency must not exceed the maximum specified clock frequency of the device. 6. this specification applies to any time the fll reference source or reference divider is changed, trim value is changed, dmx32 bit is changed, drs bits are changed, or changing from fll disabled (blpe, blpi) to fll enabled (fei, fee, fbe, fbi). if a crystal/resonator is being used as the reference, this specification assumes it is already running. 7. excludes any oscillator currents that are also consuming power while pll is in operation. 8. this specification applies to any time the pll vco divider or reference divider is changed, or changing from pll disabled (blpe, blpi) to pll enabled (pbe, pee). if a crystal/resonator is being used as the reference, this specification assumes it is already running. 9. accumulated jitter will depend on vco frequency and vdiv. 6.3.2 oscillator electrical specifications this section provides the electrical characteristics of the module. 6.3.2.1 oscillator dc electrical specifications table 15. oscillator dc electrical specifications symbol description min. typ. max. unit notes v dd supply voltage 1.71 3.6 v i ddosc supply current low-power mode (hgo=0) ? 32 khz ? 4 mhz ? 8 mhz (range=01) ? 16 mhz ? 24 mhz ? 32 mhz 500 200 300 950 1.2 1.5 na a a a ma ma 1 table continues on the next page... peripheral operating requirements and behaviors k60 sub-family data sheet data sheet, rev. 3, 2/2012. 30 preliminary freescale semiconductor, inc.
table 15. oscillator dc electrical specifications (continued) symbol description min. typ. max. unit notes i ddosc supply current high gain mode (hgo=1) ? 32 khz ? 4 mhz ? 8 mhz (range=01) ? 16 mhz ? 24 mhz ? 32 mhz 25 400 500 2.5 3 4 a a a ma ma ma 1 c x extal load capacitance 2 , 3 c y xtal load capacitance 2 , 3 r f feedback resistor low-frequency, low-power mode (hgo=0) m 2 , 4 feedback resistor low-frequency, high-gain mode (hgo=1) 10 m feedback resistor high-frequency, low-power mode (hgo=0) m feedback resistor high-frequency, high-gain mode (hgo=1) 1 m r s series resistor low-frequency, low-power mode (hgo=0) k series resistor low-frequency, high-gain mode (hgo=1) 200 k series resistor high-frequency, low-power mode (hgo=0) k series resistor high-frequency, high-gain mode (hgo=1) 0 k v pp 5 peak-to-peak amplitude of oscillation (oscillator mode) low-frequency, low-power mode (hgo=0) 0.6 v peak-to-peak amplitude of oscillation (oscillator mode) low-frequency, high-gain mode (hgo=1) v dd v peak-to-peak amplitude of oscillation (oscillator mode) high-frequency, low-power mode (hgo=0) 0.6 v peak-to-peak amplitude of oscillation (oscillator mode) high-frequency, high-gain mode (hgo=1) v dd v 1. v dd =3.3 v, temperature =25 c 2. see crystal or resonator manufacturer's recommendation 3. c x ,c y can be provided by using either the integrated capacitors or by using external components. 4. when low power mode is selected, r f is integrated and must not be attached externally. peripheral operating requirements and behaviors k60 sub-family data sheet data sheet, rev. 3, 2/2012. freescale semiconductor, inc. preliminary 31
5. the extal and xtal pins should only be connected to required oscillator components and must not be connected to any other devices. 6.3.2.2 oscillator frequency specifications table 16. oscillator frequency specifications symbol description min. typ. max. unit notes f osc_lo oscillator crystal or resonator frequency low frequency mode (mcg_c2[range]=00) 32 40 khz f osc_hi_1 oscillator crystal or resonator frequency high frequency mode (low range) (mcg_c2[range]=01) 3 8 mhz 1 f osc_hi_2 oscillator crystal or resonator frequency high frequency mode (high range) (mcg_c2[range]=1x) 8 32 mhz f ec_extal input clock frequency (external clock mode) 60 mhz 2 , 3 t dc_extal input clock duty cycle (external clock mode) 40 50 60 % t cst crystal startup time 32 khz low-frequency, low-power mode (hgo=0) 1000 ms 4 , 5 crystal startup time 32 khz low-frequency, high-gain mode (hgo=1) 500 ms crystal startup time 8 mhz high-frequency (mcg_c2[range]=01), low-power mode (hgo=0) 0.6 ms crystal startup time 8 mhz high-frequency (mcg_c2[range]=01), high-gain mode (hgo=1) 1 ms 1. frequencies less than 8 mhz are not in the pll range. 2. other frequency limits may apply when external clock is being used as a reference for the fll or pll. 3. when transitioning from fbe to fei mode, restrict the frequency of the input clock so that, when it is divided by frdiv, it remains within the limits of the dco input clock frequency. 4. proper pc board layout procedures must be followed to achieve specifications. 5. crystal startup time is defined as the time between the oscillator being enabled and the oscinit bit in the mcg_s register being set. 6.3.3 32khz oscillator electrical characteristics this section describes the module electrical characteristics. 6.3.3.1 32khz oscillator dc electrical specifications table 17. 32khz oscillator dc electrical specifications symbol description min. typ. max. unit v bat supply voltage 1.71 3.6 v r f internal feedback resistor 100 m table continues on the next page... peripheral operating requirements and behaviors k60 sub-family data sheet data sheet, rev. 3, 2/2012. 32 preliminary freescale semiconductor, inc.
table 17. 32khz oscillator dc electrical specifications (continued) symbol description min. typ. max. unit c para parasitical capacitance of extal32 and xtal32 5 7 pf v pp 1 peak-to-peak amplitude of oscillation 0.6 v 1. the extal32 and xtal32 pins should only be connected to required oscillator components and must not be connected to any other devices. 6.3.3.2 32khz oscillator frequency specifications table 18. 32khz oscillator frequency specifications symbol description min. typ. max. unit notes f osc_lo oscillator crystal 32.768 khz t start crystal start-up time 1000 ms 1 1. proper pc board layout procedures must be followed to achieve specifications. 6.4 memories and memory interfaces 6.4.1 flash (ftfe) electrical specifications this section describes the electrical characteristics of the ftfe module. 6.4.1.1 flash timing specifications program and erase the following specifications represent the amount of time the internal charge pumps are active and do not include command overhead. table 19. nvm program/erase timing specifications symbol description min. typ. max. unit notes t hvpgm4 program phrase high-voltage time 7.5 tbd s t hversscr erase flash sector high-voltage time 13 tbd ms 1 t hversblk erase flash block high-voltage time 425 tbd ms 1 1. maximum time based on expectations at cycling end-of-life. peripheral operating requirements and behaviors k60 sub-family data sheet data sheet, rev. 3, 2/2012. freescale semiconductor, inc. preliminary 33
6.4.1.2 flash timing specifications commands table 20. flash command timing specifications symbol description min. typ. max. unit notes t rd1blk read 1s block execution time 1.5 tbd ms t rd1sec4k read 1s section execution time (4kb flash) 50 tbd s 1 t pgmchk program check execution time 35 tbd s 1 t rdrsrc read resource execution time 35 tbd s 1 t pgm8 program phrase execution time 65 tbd s t ersblk erase flash block execution time 450 tbd ms 2 t ersscr erase flash sector execution time 15 tbd ms 2 t pgmsec4k program section execution time (4kb flash) 20 tbd ms t rd1all read 1s all blocks execution time 1.5 tbd ms t rdonce read once execution time 17 tbd s 1 t pgmonce program once execution time 65 tbd s t ersall erase all blocks execution time 900 tbd ms 2 t vfykey verify backdoor access key execution time 25 tbd s 1 t swapx01 t swapx02 t swapx04 t swapx08 swap control execution time ? control code 0x01 ? control code 0x02 ? control code 0x04 ? control code 0x08 185 65 65 25 tbd tbd tbd tbd s s s s t pgmpart program partition for eeprom execution time tbd tbd ms t setram64k t setram128k t setram256k t setram512k set flexram function execution time: ? 64 kb eeprom backup ? 128 kb eeprom backup ? 256 kb eeprom backup ? 512 kb eeprom backup tbd tbd tbd tbd tbd tbd tbd tbd ms ms ms ms t eewr8bers byte-write to erased flexram location execution time 100 tbd s 3 t eewr8b64k t eewr8b128k t eewr8b256k t eewr8b512k byte-write to flexram execution time: ? 64 kb eeprom backup ? 128 kb eeprom backup ? 256 kb eeprom backup ? 512 kb eeprom backup tbd tbd tbd tbd tbd tbd tbd tbd ms ms ms ms t eewr16bers 16-bit write to erased flexram location execution time 100 tbd s table continues on the next page... peripheral operating requirements and behaviors k60 sub-family data sheet data sheet, rev. 3, 2/2012. 34 preliminary freescale semiconductor, inc.
table 20. flash command timing specifications (continued) symbol description min. typ. max. unit notes t eewr16b64k t eewr16b128k t eewr16b256k t eewr16b512k 16-bit write to flexram execution time: ? 64 kb eeprom backup ? 128 kb eeprom backup ? 256 kb eeprom backup ? 512 kb eeprom backup tbd tbd tbd tbd tbd tbd tbd tbd ms ms ms ms t eewr32bers 32-bit write to erased flexram location execution time 200 tbd s t eewr32b64k t eewr32b128k t eewr32b256k t eewr32b512k 32-bit-write to flexram execution time: ? 64 kb eeprom backup ? 128 kb eeprom backup ? 256 kb eeprom backup ? 512 kb eeprom backup tbd tbd tbd tbd tbd tbd tbd tbd ms ms ms ms 1. assumes 25mhz flash clock frequency. 2. maximum times for erase parameters based on expectations at cycling end-of-life. 3. for byte-writes to an erased flexram location, the aligned word containing the byte must be erased. 6.4.1.3 flash (ftfe) current and power specfications table 21. flash (ftfe) current and power specfications symbol description typ. unit i dd_pgm worst case programming current in program flash 10 ma 6.4.1.4 reliability specifications table 22. nvm reliability specifications symbol description min. typ. 1 max. unit notes program flash t nvmretp10k data retention after up to 10 k cycles 5 50 years 2 t nvmretp1k data retention after up to 1 k cycles 10 100 years 2 t nvmretp100 data retention after up to 100 cycles 15 100 years 2 n nvmcycp cycling endurance 10 k 35 k cycles 3 data flash t nvmretd10k data retention after up to 10 k cycles 5 50 years 2 t nvmretd1k data retention after up to 1 k cycles 10 100 years 2 t nvmretd100 data retention after up to 100 cycles 15 100 years 2 n nvmcycd cycling endurance 10 k 35 k cycles 3 table continues on the next page... peripheral operating requirements and behaviors k60 sub-family data sheet data sheet, rev. 3, 2/2012. freescale semiconductor, inc. preliminary 35
table 22. nvm reliability specifications (continued) symbol description min. typ. 1 max. unit notes flexram as eeprom t nvmretee100 data retention up to 100% of write endurance 5 50 years 2 t nvmretee10 data retention up to 10% of write endurance 10 100 years 2 t nvmretee1 data retention up to 1% of write endurance 15 100 years 2 n nvmwree16 n nvmwree128 n nvmwree512 n nvmwree4k n nvmwree32k write endurance ? eeprom backup to flexram ratio = 16 ? eeprom backup to flexram ratio = 128 ? eeprom backup to flexram ratio = 512 ? eeprom backup to flexram ratio = 4096 ? eeprom backup to flexram ratio = 32,768 tbd tbd tbd tbd tbd tbd tbd tbd tbd tbd writes writes writes writes writes 4 1. typical data retention values are based on measured response accelerated at high temperature and derated to a constant 25c profile. engineering bulletin eb618 does not apply to this technology. 2. data retention is based on t javg = 55c (temperature profile over the lifetime of the application). 3. cycling endurance represents number of program/erase cycles at -40c t j 125c. 4. write endurance represents the number of writes to each flexram location at -40c tj 125c influenced by the cycling endurance of the flexnvm (same value as data flash) and the allocated eeprom backup per subsystem. minimum and typical values assume all byte-writes to flexram. 6.4.1.5 write endurance to flexram for eeprom tbd 6.4.2 ezport switching specifications table 23. ezport switching specifications num description min. max. unit operating voltage 1.71 3.6 v ep1 ezp_ck frequency of operation (all commands except read) f sys /2 mhz ep1a ezp_ck frequency of operation (read command) f sys /8 mhz ep2 ezp_cs negation to next ezp_cs assertion 2 x t ezp_ck ns ep3 ezp_cs input valid to ezp_ck high (setup) 5 ns ep4 ezp_ck high to ezp_cs input invalid (hold) 5 ns ep5 ezp_d input valid to ezp_ck high (setup) 2 ns ep6 ezp_ck high to ezp_d input invalid (hold) 5 ns ep7 ezp_ck low to ezp_q output valid 16 ns table continues on the next page... peripheral operating requirements and behaviors k60 sub-family data sheet data sheet, rev. 3, 2/2012. 36 preliminary freescale semiconductor, inc.
table 23. ezport switching specifications (continued) num description min. max. unit ep8 ezp_ck low to ezp_q output invalid (hold) 0 ns ep9 ezp_cs negation to ezp_q tri-state 12 ns ep2 ep3 ep4 ep5 ep6 ep7 ep8 ep9 ezp_ck ezp_cs ezp_q (output) ezp_d (input) figure 10. ezport timing diagram 6.4.3 nfc specifications the nand flash controller (nfc) implements the interface to standard nand flash memory devices. this section describes the timing parameters of the nfc. in the following table: ? t h is the flash clock high time and ? t l is flash clock low time, which are defined as: input clock t scaler = nfc t = h t l t + the scaler value is derived from the fractional divider specified in the sim's clkdiv4 register: scaler = sim_clkdiv4[nfcfrac] + 1 sim_clkdiv4[nfcdiv] + 1 peripheral operating requirements and behaviors k60 sub-family data sheet data sheet, rev. 3, 2/2012. freescale semiconductor, inc. preliminary 37
in case the reciprocal of scaler is an integer, the duty cycle of nfc clock is 50%, means t h = t l . in case the reciprocal of scaler is not an integer: (1 + scaler / 2) x = l t nfc t 2 (1 C scaler / 2) x = h t nfc t 2 for example, if scaler is 0.2, then t h = t l = t nfc /2. t nfc t h t l however, if scaler is 0.667, then t l = 2/3 x t nfc and t h = 1/3 x t nfc . t nfc t h t l note the reciprocal of scaler must be a multiple of 0.5. for example, 1, 1.5, 2, 2.5, etc. table 24. nfc specifications num description min. max. unit t cls nfc_cle setup time 2t h + t l C 1 ns t clh nfc_cle hold time t h + t l C 1 ns t cs nfc_cen setup time 2t h + t l C 1 ns t ch nfc_cen hold time t h + t l ns t wp nfc_wp pulse width t l C 1 ns t als nfc_ale setup time 2t h + t l ns t alh nfc_ale hold time t h + t l ns t ds data setup time t l C 1 ns t dh data hold time t h C 1 ns t wc write cycle time t h + t l C 1 ns t wh nfc_we hold time t h C 1 ns t rr ready to nfc_re low 4t h + 3t l + 90 ns t rp nfc_re pulse width t l + 1 ns table continues on the next page... peripheral operating requirements and behaviors k60 sub-family data sheet data sheet, rev. 3, 2/2012. 38 preliminary freescale semiconductor, inc.
table 24. nfc specifications (continued) num description min. max. unit t rc read cycle time t l + t h C 1 ns t reh nfc_re high hold time t h C 1 ns t is data input setup time 11 ns tcs tchtwp tds tdh tcls tclh nfc_cle nfc_cen nfc_we nfc_ion figure 11. command latch cycle timing tcs tchtwp tds tdh tals talh address nfc_ale nfc_cen nfc_we nfc_ion figure 12. address latch cycle timing tcs tch twp tds tdh data data data twc twh nfc_cen nfc_we nfc_ion figure 13. write data latch cycle timing peripheral operating requirements and behaviors k60 sub-family data sheet data sheet, rev. 3, 2/2012. freescale semiconductor, inc. preliminary 39
tch trp data data data trc treh tis trr nfc_cen nfc_re nfc_ion nfc_rb figure 14. read data latch cycle timing in non-fast mode tch trp data data data trc treh tis trr nfc_cen nfc_re nfc_ion nfc_rb figure 15. read data latch cycle timing in fast mode 6.4.4 flexbus switching specifications all processor bus timings are synchronous; input setup/hold and output delay are given in respect to the rising edge of a reference clock, fb_clk. the fb_clk frequency may be the same as the internal system bus frequency or an integer divider of that frequency. the following timing numbers indicate when data is latched or driven onto the external bus, relative to the flexbus output clock (fb_clk). all other timing relationships can be derived from these values. table 25. flexbus limited voltage range switching specifications num description min. max. unit notes operating voltage 2.7 3.6 v frequency of operation fb_clk mhz fb1 clock period 20 ns table continues on the next page... peripheral operating requirements and behaviors k60 sub-family data sheet data sheet, rev. 3, 2/2012. 40 preliminary freescale semiconductor, inc.
table 25. flexbus limited voltage range switching specifications (continued) num description min. max. unit notes fb2 address, data, and control output valid 11.5 ns 1 fb3 address, data, and control output hold 0.5 ns 1 fb4 data and fb_ta input setup 8.5 ns 2 fb5 data and fb_ta input hold 0.5 ns 2 1. specification is valid for all fb_ad[31:0], fb_be/bwe n , fb_cs n , fb_oe, fb_r/ w, fb_tbst, fb_tsiz[1:0], fb_ale, and fb_ts. 2. specification is valid for all fb_ad[31:0] and fb_ta. table 26. flexbus full voltage range switching specifications num description min. max. unit notes operating voltage 1.71 3.6 v frequency of operation fb_clk mhz fb1 clock period 1/fb_clk ns fb2 address, data, and control output valid 13.5 ns 1 fb3 address, data, and control output hold 0 ns 1 fb4 data and fb_ta input setup 13.7 ns 2 fb5 data and fb_ta input hold 0.5 ns 2 1. specification is valid for all fb_ad[31:0], fb_be/bwe n , fb_cs n , fb_oe, fb_r/ w, fb_tbst, fb_tsiz[1:0], fb_ale, and fb_ts. 2. specification is valid for all fb_ad[31:0] and fb_ta. peripheral operating requirements and behaviors k60 sub-family data sheet data sheet, rev. 3, 2/2012. freescale semiconductor, inc. preliminary 41
address address data tsiz aa=1 aa=0 aa=1 aa=0 fb1 fb3 fb5 fb4 fb4 fb5 fb2 fb_clk fb_a[y] fb_d[x] fb_rw fb_ts fb_ale fb_csn fb_oen fb_ben fb_ta fb_tsiz[1:0] figure 16. flexbus read timing diagram peripheral operating requirements and behaviors k60 sub-family data sheet data sheet, rev. 3, 2/2012. 42 preliminary freescale semiconductor, inc.
address address data tsiz aa=1 aa=0 aa=1 aa=0 fb1 fb3 fb4 fb5 fb2 fb_clk fb_a[y] fb_d[x] fb_rw fb_ts fb_ale fb_csn fb_oen fb_ben fb_ta fb_tsiz[1:0] figure 17. flexbus write timing diagram 6.5 security and integrity modules there are no specifications necessary for the device's security and integrity modules. 6.6 analog peripheral operating requirements and behaviors k60 sub-family data sheet data sheet, rev. 3, 2/2012. freescale semiconductor, inc. preliminary 43
6.6.1 adc electrical specifications the 16-bit accuracy specifications listed in table 27 and table 28 are achievable on the differential pins adcx_dp0, adcx_dm0. the adcx_dp2 and adcx_dm2 adc inputs are connected to the pga outputs and are not direct device pins. accuracy specifications for these pins are defined in table 29 and table 30 . all other adc channels meet the 13-bit differential/12-bit single-ended accuracy specifications. 6.6.1.1 16-bit adc operating conditions table 27. 16-bit adc operating conditions symbol description conditions min. typ. 1 max. unit notes v dda supply voltage absolute 1.71 3.6 v v dda supply voltage delta to v dd (v dd - v dda ) -100 0 +100 mv 2 v ssa ground voltage delta to v ss (v ss - v ssa ) -100 0 +100 mv 2 v refh adc reference voltage high 1.13 v dda v dda v v refl reference voltage low v ssa v ssa v ssa v v adin input voltage v refl v refh v c adin input capacitance ? 16 bit modes ? 8/10/12 bit modes 8 4 10 5 pf r adin input resistance 2 5 k r as analog source resistance 13/12 bit modes f adck < 4mhz 5 k 3 f adck adc conversion clock frequency 13 bit modes 1.0 18.0 mhz 4 f adck adc conversion clock frequency 16 bit modes 2.0 12.0 mhz 4 table continues on the next page... peripheral operating requirements and behaviors k60 sub-family data sheet data sheet, rev. 3, 2/2012. 44 preliminary freescale semiconductor, inc.
table 27. 16-bit adc operating conditions (continued) symbol description conditions min. typ. 1 max. unit notes c rate adc conversion rate 13 bit modes no adc hardware averaging continuous conversions enabled, subsequent conversion time 20.000 818.330 ksps 5 c rate adc conversion rate 16 bit modes no adc hardware averaging continuous conversions enabled, subsequent conversion time 37.037 461.467 ksps 5 1. typical values assume v dda = 3.0 v, temp = 25c, f adck = 1.0 mhz unless otherwise stated. typical values are for reference only and are not tested in production. 2. dc potential difference. 3. this resistance is external to mcu. the analog source resistance should be kept as low as possible in order to achieve the best results. the results in this datasheet were derived from a system which has <8 analog source resistance. the r as / c as time constant should be kept to <1ns. 4. to use the maximum adc conversion clock frequency, the adhsc bit should be set and the adlpc bit should be clear. 5. for guidelines and examples of conversion rate calculation, download the adc calculator tool: http://cache.freescale.com/ files/soft_dev_tools/software/app_software/converters/adc_calculator_cnv.zip?fpsp=1 r as v as c as z as v adin z adin r adin r adin r adin r adin c adin pad leakage due to input protection input pin input pin input pin input pin simplified input pin equivalent circuit simplified channel select circuit adc sar engine figure 18. adc input impedance equivalency diagram peripheral operating requirements and behaviors k60 sub-family data sheet data sheet, rev. 3, 2/2012. freescale semiconductor, inc. preliminary 45
6.6.1.2 16-bit adc electrical characteristics table 28. 16-bit adc characteristics (v refh = v dda , v refl = v ssa ) symbol description conditions 1 min. typ. 2 max. unit notes i dda_adc supply current 0.215 1.7 ma 3 f adack adc asynchronous clock source ? adlpc=1, adhsc=0 ? adlpc=1, adhsc=1 ? adlpc=0, adhsc=0 ? adlpc=0, adhsc=1 1.2 3.0 2.4 4.4 2.4 4.0 5.2 6.2 3.9 7.3 6.1 9.5 mhz mhz mhz mhz t adack = 1/ f adack sample time see reference manual chapter for sample times tue total unadjusted error ? 12 bit modes ? <12 bit modes 4 1.4 6.8 2.1 lsb 4 5 dnl differential non- linearity ? 12 bit modes ? <12 bit modes 0.7 0.2 -1.1 to +1.9 -0.3 to 0.5 lsb 4 5 inl integral non- linearity ? 12 bit modes ? <12 bit modes 1.0 0.5 -2.7 to +1.9 -0.7 to +0.5 lsb 4 5 e fs full-scale error ? 12 bit modes ? <12 bit modes -4 -1.4 -5.4 -1.8 lsb 4 v adin = v dda 5 e q quantization error ? 16 bit modes ? 13 bit modes -1 to 0 0.5 lsb 4 enob effective number of bits 16 bit differential mode ? avg=32 ? avg=4 16 bit single-ended mode ? avg=32 ? avg=4 12.8 11.9 12.2 11.4 14.5 13.8 13.9 13.1 bits bits bits bits 6 sinad signal-to-noise plus distortion see enob 6.02 enob + 1.76 db thd total harmonic distortion 16 bit differential mode ? avg=32 16 bit single-ended mode ? avg=32 C94 -85 db db 7 table continues on the next page... peripheral operating requirements and behaviors k60 sub-family data sheet data sheet, rev. 3, 2/2012. 46 preliminary freescale semiconductor, inc.
table 28. 16-bit adc characteristics (v refh = v dda , v refl = v ssa ) (continued) symbol description conditions 1 min. typ. 2 max. unit notes sfdr spurious free dynamic range 16 bit differential mode ? avg=32 16 bit single-ended mode ? avg=32 82 78 95 90 db db 7 e il input leakage error i in r as mv i in = leakage current (refer to the mcu's voltage and current operating ratings) temp sensor slope C40c to 105c 1.715 mv/c v temp25 temp sensor voltage 25c 719 mv 1. all accuracy numbers assume the adc is calibrated with v refh = v dda 2. typical values assume v dda = 3.0 v, temp = 25c, f adck = 2.0 mhz unless otherwise stated. typical values are for reference only and are not tested in production. 3. the adc supply current depends on the adc conversion clock speed, conversion rate and the adlpc bit (low power). for lowest power operation the adlpc bit should be set, the hsc bit should be clear with 1mhz adc conversion clock speed. 4. 1 lsb = (v refh - v refl )/2 n 5. adc conversion clock <16mhz, max hardware averaging (avge = %1, avgs = %11) 6. input data is 100 hz sine wave. adc conversion clock <12mhz. 7. input data is 1 khz sine wave. adc conversion clock <12mhz. peripheral operating requirements and behaviors k60 sub-family data sheet data sheet, rev. 3, 2/2012. freescale semiconductor, inc. preliminary 47
figure 19. typical enob vs. adc_clk for 16-bit differential mode figure 20. typical enob vs. adc_clk for 16-bit single-ended mode peripheral operating requirements and behaviors k60 sub-family data sheet data sheet, rev. 3, 2/2012. 48 preliminary freescale semiconductor, inc.
6.6.1.3 16-bit adc with pga operating conditions table 29. 16-bit adc with pga operating conditions symbol description conditions min. typ. 1 max. unit notes v dda supply voltage absolute 1.71 3.6 v v refpga pga ref voltage vref_ou t vref_ou t vref_ou t v 2 , 3 v adin input voltage v ssa v dda v v cm input common mode range v ssa v dda v r pgad differential input impedance gain = 1, 2, 4, 8 gain = 16, 32 gain = 64 128 64 32 k in+ to in- 4 r as analog source resistance 100 5 t s adc sampling time 1.25 s 6 c rate adc conversion rate 13 bit modes no adc hardware averaging continuous conversions enabled peripheral clock = 50 mhz 18.484 450 ksps 7 16 bit modes no adc hardware averaging continuous conversions enabled peripheral clock = 50 mhz 37.037 250 ksps 8 1. typical values assume v dda = 3.0 v, temp = 25c, f adck = 6 mhz unless otherwise stated. typical values are for reference only and are not tested in production. 2. adc must be configured to use the internal voltage reference (vref_out) 3. pga reference is internally connected to the vref_out pin. if the user wishes to drive vref_out with a voltage other than the output of the vref module, the vref module must be disabled. 4. for single ended configurations the input impedance of the driven input is r pgad /2 5. the analog source resistance (r as ), external to mcu, should be kept as minimum as possible. increased r as causes drop in pga gain without affecting other performances. this is not dependent on adc clock frequency. 6. the minimum sampling time is dependent on input signal frequency and adc mode of operation. a minimum of 1.25s time should be allowed for f in =4 khz at 16-bit differential mode. recommended adc setting is: adlsmp=1, adlsts=2 at 8 mhz adc clock. 7. adc clock = 18 mhz, adlsmp = 1, adlst = 00, adhsc = 1 8. adc clock = 12 mhz, adlsmp = 1, adlst = 01, adhsc = 1 peripheral operating requirements and behaviors k60 sub-family data sheet data sheet, rev. 3, 2/2012. freescale semiconductor, inc. preliminary 49
6.6.1.4 16-bit adc with pga characteristics table 30. 16-bit adc with pga characteristics symbol description conditions min. typ. 1 max. unit notes i dda_pga supply current low power (adc_pga[pgalpb]=0) 420 644 a 2 i dc_pga input dc current a 3 gain =1, v refpga =1.2v, v cm =0.5v 1.54 a gain =64, v refpga =1.2v, v cm =0.1v 0.57 a g gain 4 ? pgag=0 ? pgag=1 ? pgag=2 ? pgag=3 ? pgag=4 ? pgag=5 ? pgag=6 0.95 1.9 3.8 7.6 15.2 30.0 58.8 1 2 4 8 16 31.6 63.3 1.05 2.1 4.2 8.4 16.6 33.2 67.8 r as < 100 bw input signal bandwidth ? 16-bit modes ? < 16-bit modes 4 40 khz khz psrr power supply rejection ratio gain=1 -84 db v dda = 3v 100mv, f vdda = 50hz, 60hz cmrr common mode rejection ratio ? gain=1 ? gain=64 -84 -85 db db v cm = 500mvpp, f vcm = 50hz, 100hz v ofs input offset voltage ? chopping disabled (adc_pga[pgachpb] =1) ? chopping enabled (adc_pga[pgachpb] =0) 2.4 0.2 tbd mv mv output offset = v ofs *(gain+1) t gsw gain switching settling time 10 s 5 dg/dt gain drift over temperature ? gain=1 ? gain=64 tbd tbd tbd tbd ppm/c ppm/c 0 to 50c dv ofs /dt offset drift over temperature gain=1 tbd tbd ppm/c 0 to 50c, adc averaging=32 dg/dv dda gain drift over supply voltage ? gain=1 ? gain=64 tbd tbd tbd tbd %/v %/v v dda from 1.71 to 3.6v table continues on the next page... peripheral operating requirements and behaviors k60 sub-family data sheet data sheet, rev. 3, 2/2012. 50 preliminary freescale semiconductor, inc.
table 30. 16-bit adc with pga characteristics (continued) symbol description conditions min. typ. 1 max. unit notes e il input leakage error all modes i in r as mv i in = leakage current (refer to the mcu's voltage and current operating ratings) v pp,diff maximum differential input signal swing where v x = v refpga 0.583 v 6 snr signal-to-noise ratio ? gain=1 ? gain=64 80 52 90 66 db db 16-bit differential mode, average=32 thd total harmonic distortion ? gain=1 ? gain=64 85 49 100 95 db db 16-bit differential mode, average=32, f in =100hz sfdr spurious free dynamic range ? gain=1 ? gain=64 85 53 105 88 db db 16-bit differential mode, average=32, f in =100hz enob effective number of bits ? gain=1, average=4 ? gain=1, average=8 ? gain=64, average=4 ? gain=64, average=8 ? gain=1, average=32 ? gain=2, average=32 ? gain=4, average=32 ? gain=8, average=32 ? gain=16, average=32 ? gain=32, average=32 ? gain=64, average=32 11.6 tbd 7.2 tbd 12.8 11.0 7.9 7.3 6.8 6.8 7.5 13.4 12.7 9.6 8.7 14.5 14.3 13.8 13.1 12.5 11.5 10.6 bits bits bits bits bits bits bits bits bits bits bits 16-bit differential mode,f in =100h z sinad signal-to-noise plus distortion ratio see enob 6.02 enob + 1.76 db 1. typical values assume v dda =3.0v, temp=25c, f adck =6mhz unless otherwise stated. 2. this current is a pga module adder, in addition to and adc conversion currents. 3. between in+ and in-. the pga draws a dc current from the input terminals. the magnitude of the dc current is a strong function of input common mode voltage (v cm ) and the pga gain. 4. gain = 2 pgag 5. after changing the pga gain setting, a minimum of 2 adc+pga conversions should be ignored. peripheral operating requirements and behaviors k60 sub-family data sheet data sheet, rev. 3, 2/2012. freescale semiconductor, inc. preliminary 51
6. limit the input signal swing so that the pga does not saturate during operation. input signal swing is dependent on the pga reference voltage and gain setting. 6.6.2 cmp and 6-bit dac electrical specifications table 31. comparator and 6-bit dac electrical specifications symbol description min. typ. max. unit v dd supply voltage 1.71 3.6 v i ddhs supply current, high-speed mode (en=1, pmode=1) 200 a i ddls supply current, low-speed mode (en=1, pmode=0) 20 a v ain analog input voltage v ss C 0.3 v dd v v aio analog input offset voltage 20 mv v h analog comparator hysteresis 1 ? cr0[hystctr] = 00 ? cr0[hystctr] = 01 ? cr0[hystctr] = 10 ? cr0[hystctr] = 11 5 10 20 30 mv mv mv mv v cmpoh output high v dd C 0.5 v v cmpol output low 0.5 v t dhs propagation delay, high-speed mode (en=1, pmode=1) 20 50 200 ns t dls propagation delay, low-speed mode (en=1, pmode=0) 80 250 600 ns analog comparator initialization delay 2 40 s i dac6b 6-bit dac current adder (enabled) 7 a inl 6-bit dac integral non-linearity C0.5 0.5 lsb 3 dnl 6-bit dac differential non-linearity C0.3 0.3 lsb 1. typical hysteresis is measured with input voltage range limited to 0.6 to v dd -0.6v. 2. comparator initialization delay is defined as the time between software writes to change control inputs (writes to dacen, vrsel, psel, msel, vosel) and the comparator output settling to a stable level. 3. 1 lsb = v reference /64 peripheral operating requirements and behaviors k60 sub-family data sheet data sheet, rev. 3, 2/2012. 52 preliminary freescale semiconductor, inc.
0.04 0.05 0.06 0.07 0.08 p hystereris (v) 00 01 10 hystctr setting 0 0.01 0.02 0.03 0.1 0.4 0.7 1 1.3 1.6 1.9 2.2 2.5 2.8 3.1 cm 10 11 vin level (v) figure 21. typical hysteresis vs. vin level (vdd=3.3v, pmode=0) peripheral operating requirements and behaviors k60 sub-family data sheet data sheet, rev. 3, 2/2012. freescale semiconductor, inc. preliminary 53
0 08 0.1 0.12 0.14 0.16 0.18 p hystereris (v) 00 01 10 hystctr setting 0 0.02 0.04 0.06 0.08 0.1 0.4 0.7 1 1.3 1.6 1.9 2.2 2.5 2.8 3.1 cm p 10 11 vin level (v) figure 22. typical hysteresis vs. vin level (vdd=3.3v, pmode=1) 6.6.3 12-bit dac electrical characteristics 6.6.3.1 12-bit dac operating requirements table 32. 12-bit dac operating requirements symbol desciption min. max. unit notes v dda supply voltage 1.71 3.6 v v dacr reference voltage 1.13 3.6 v 1 t a temperature ?40 105 c c l output load capacitance 100 pf 2 i l output load current 1 ma 1. the dac reference can be selected to be vdda or the voltage output of the vref module (vref_out) 2. a small load capacitance (47 pf) can improve the bandwidth performance of the dac peripheral operating requirements and behaviors k60 sub-family data sheet data sheet, rev. 3, 2/2012. 54 preliminary freescale semiconductor, inc.
6.6.3.2 12-bit dac operating behaviors table 33. 12-bit dac operating behaviors symbol description min. typ. max. unit notes i dda_dacl p supply current low-power mode 150 a i dda_dac hp supply current high-speed mode 700 a t daclp full-scale settling time (0x080 to 0xf7f) low-power mode 100 200 s 1 t dachp full-scale settling time (0x080 to 0xf7f) high-power mode 15 30 s 1 t ccdaclp code-to-code settling time (0xbf8 to 0xc08) low-power mode and high-speed mode 0.7 1 s 1 v dacoutl dac output voltage range low high- speed mode, no load, dac set to 0x000 100 mv v dacouth dac output voltage range high high- speed mode, no load, dac set to 0xfff v dacr ?100 v dacr mv inl integral non-linearity error high speed mode 8 lsb 2 dnl differential non-linearity error v dacr > 2 v 1 lsb 3 dnl differential non-linearity error v dacr = vref_out 1 lsb 4 v offset offset error 0.4 0.8 %fsr 5 e g gain error 0.1 0.6 %fsr 5 psrr power supply rejection ratio, v dda > = 2.4 v 60 90 db t co temperature coefficient offset voltage 3.7 v/c 6 t ge temperature coefficient gain error 0.000421 %fsr/c rop output resistance load = 3 k 250 sr slew rate -80h f7fh 80h ? high power (sp hp ) ? low power (sp lp ) 1.2 0.05 1.7 0.12 v/s ct channel to channel cross talk -80 db bw 3db bandwidth ? high power (sp hp ) ? low power (sp lp ) 550 40 khz 1. settling within 1 lsb 2. the inl is measured for 0+100mv to v dacr ?100 mv 3. the dnl is measured for 0+100 mv to v dacr ?100 mv 4. the dnl is measured for 0+100mv to v dacr ?100 mv with v dda > 2.4v 5. calculated by a best fit curve from v ss +100 mv to v dacr ?100 mv peripheral operating requirements and behaviors k60 sub-family data sheet data sheet, rev. 3, 2/2012. freescale semiconductor, inc. preliminary 55
6. vdda = 3.0v, reference select set for vdda (dacx_co:dacrfs = 1), high power mode(dacx_c0:lpen = 0), dac set to 0x800, temp range from -40c to 105c figure 23. typical inl error vs. digital code peripheral operating requirements and behaviors k60 sub-family data sheet data sheet, rev. 3, 2/2012. 56 preliminary freescale semiconductor, inc.
figure 24. offset at half scale vs. temperature 6.6.4 voltage reference electrical specifications table 34. vref full-range operating requirements symbol description min. max. unit notes v dda supply voltage 1.71 3.6 v t a temperature ?40 105 c c l output load capacitance 100 nf 1 , 2 1. c l must be connected to vref_out if the vref_out functionality is being used for either an internal or external reference. 2. the load capacitance should not exceed +/-25% of the nominal specified c l value over the operating temperature range of the device. peripheral operating requirements and behaviors k60 sub-family data sheet data sheet, rev. 3, 2/2012. freescale semiconductor, inc. preliminary 57
table 35. vref full-range operating behaviors symbol description min. typ. max. unit notes v out voltage reference output with factory trim at nominal v dda and temperature=25c 1.1965 1.2 1.2027 v v out voltage reference output with factory trim 1.1584 1.2376 v v out voltage reference output user trim 1.198 1.202 v v step voltage reference trim step 0.5 mv v tdrift temperature drift (vmax -vmin across the full temperature range) 80 mv i bg bandgap only current 80 a 1 i tr high-power buffer current tbd ma 1 v load load regulation ? current = + 1.0 ma ? current = - 1.0 ma 2 5 mv 1 , 2 t stup buffer startup time 100 s v vdrift voltage drift (vmax -vmin across the full voltage range) 2 mv 1 1. see the chip's reference manual for the appropriate settings of the vref status and control register. 2. load regulation voltage is the difference between the vref_out voltage with no load vs. voltage with defined load table 36. vref limited-range operating requirements symbol description min. max. unit notes t a temperature 0 50 c table 37. vref limited-range operating behaviors symbol description min. max. unit notes v out voltage reference output with factory trim 1.173 1.225 v 6.7 timers see general switching specifications . 6.8 communication interfaces peripheral operating requirements and behaviors k60 sub-family data sheet data sheet, rev. 3, 2/2012. 58 preliminary freescale semiconductor, inc.
6.8.1 ethernet switching specifications the following timing specs are defined at the chip i/o pin and must be translated appropriately to arrive at timing specs/constraints for the physical interface. 6.8.1.1 mii signal switching specifications the following timing specs meet the requirements for mii style interfaces for a range of transceiver devices. table 38. mii signal switching specifications symbol description min. max. unit rxclk frequency 25 mhz mii1 rxclk pulse width high 35% 65% rxclk period mii2 rxclk pulse width low 35% 65% rxclk period mii3 rxd[3:0], rxdv, rxer to rxclk setup 5 ns mii4 rxclk to rxd[3:0], rxdv, rxer hold 5 ns txclk frequency 25 mhz mii5 txclk pulse width high 35% 65% txclk period mii6 txclk pulse width low 35% 65% txclk period mii7 txclk to txd[3:0], txen, txer invalid 2 ns mii8 txclk to txd[3:0], txen, txer valid 25 ns mii7mii8 valid data valid data valid data mii6 mii5 txclk (input) txd[n:0] txen txer figure 25. mii transmit signal timing diagram peripheral operating requirements and behaviors k60 sub-family data sheet data sheet, rev. 3, 2/2012. freescale semiconductor, inc. preliminary 59
mii2 mii1 mii4mii3 valid data valid data valid data rxclk (input) rxd[n:0] rxdv rxer figure 26. mii receive signal timing diagram 6.8.1.2 rmii signal switching specifications the following timing specs meet the requirements for rmii style interfaces for a range of transceiver devices. table 39. rmii signal switching specifications num description min. max. unit extal frequency (rmii input clock rmii_clk) 50 mhz rmii1 rmii_clk pulse width high 35% 65% rmii_clk period rmii2 rmii_clk pulse width low 35% 65% rmii_clk period rmii3 rxd[1:0], crs_dv, rxer to rmii_clk setup 4 ns rmii4 rmii_clk to rxd[1:0], crs_dv, rxer hold 2 ns rmii7 rmii_clk to txd[1:0], txen invalid 4 ns rmii8 rmii_clk to txd[1:0], txen valid 15 ns 6.8.2 usb electrical specifications the usb electricals for the usb on-the-go module conform to the standards documented by the universal serial bus implementers forum. for the most up-to-date standards, visit http://www.usb.org. peripheral operating requirements and behaviors k60 sub-family data sheet data sheet, rev. 3, 2/2012. 60 preliminary freescale semiconductor, inc.
6.8.3 usb dcd electrical specifications table 40. usb dcd electrical specifications symbol description min. typ. max. unit v dp_src usb_dp source voltage (up to 250 a) 0.5 0.7 v v lgc threshold voltage for logic high 0.8 2.0 v i dp_src usb_dp source current 7 10 13 a i dm_sink usb_dm sink current 50 100 150 a r dm_dwn d- pulldown resistance for data pin contact detect 14.25 24.8 k v dat_ref data detect voltage 0.25 0.325 0.4 v 6.8.4 usb vreg electrical specifications table 41. usb vreg electrical specifications symbol description min. typ. 1 max. unit notes vregin input supply voltage 2.7 5.5 v i ddon quiescent current run mode, load current equal zero, input supply (vregin) > 3.6 v 120 186 a i ddstby quiescent current standby mode, load current equal zero 1.1 1.54 a i ddoff quiescent current shutdown mode ? vregin = 5.0 v and temperature=25c ? across operating voltage and temperature 650 4 na a i loadrun maximum load current run mode 120 ma i loadstby maximum load current standby mode 1 ma v reg33out regulator output voltage input supply (vregin) > 3.6 v ? run mode ? standby mode 3 2.1 3.3 2.8 3.6 3.6 v v v reg33out regulator output voltage input supply (vregin) < 3.6 v, pass-through mode 2.1 3.6 v 2 c out external output capacitor 1.76 2.2 8.16 f esr external output capacitor equivalent series resistance 1 100 m i lim short circuit current 290 ma 1. typical values assume vregin = 5.0 v, temp = 25 c unless otherwise stated. 2. operating in pass-through mode: regulator output voltage equal to the input voltage minus a drop proportional to i load . peripheral operating requirements and behaviors k60 sub-family data sheet data sheet, rev. 3, 2/2012. freescale semiconductor, inc. preliminary 61
6.8.5 ulpi timing specifications the ulpi interface is fully compliant with the industry standard utmi+ low pin interface. control and data timing requirements for the ulpi pins are given in the following table. these timings apply to synchronous mode only. all timings are measured with respect to the clock as seen at the usb_clkin pin. table 42. ulpi timing specifications num description min. typ. max. unit usb_clkin operating frequency 60 mhz usb_clkin duty cycle 50 % u1 usb_clkin clock period 16.67 ns u2 input setup (control and data) 5 ns u3 input hold (control and data) 1 ns u4 output valid (control and data) 9.5 ns u5 output hold (control and data) 1 ns u1 u2 u3 u4 u5 usb_clkin ulpi_dir/ulpi_nxt (control input) ulpi_datan (input) ulpi_stp (control output) ulpi_datan (output) figure 27. ulpi timing diagram peripheral operating requirements and behaviors k60 sub-family data sheet data sheet, rev. 3, 2/2012. 62 preliminary freescale semiconductor, inc.
6.8.6 can switching specifications see general switching specifications . 6.8.7 dspi switching specifications (limited voltage range) the dma serial peripheral interface (dspi) provides a synchronous serial bus with master and slave operations. many of the transfer attributes are programmable. the tables below provide dspi timing characteristics for classic spi timing modes. refer to the dspi chapter of the reference manual for information on the modified transfer formats used for communicating with slower peripheral devices. table 43. master mode dspi timing (limited voltage range) num description min. max. unit notes operating voltage 2.7 3.6 v frequency of operation 30 mhz ds1 dspi_sck output cycle time 2 x t bus ns ds2 dspi_sck output high/low time (t sck /2) ? 2 (t sck /2) + 2 ns ds3 dspi_pcs n valid to dspi_sck delay (t bus x 2) ? 2 ns 1 ds4 dspi_sck to dspi_pcs n invalid delay (t bus x 2) ? 2 ns 2 ds5 dspi_sck to dspi_sout valid 8.5 ns ds6 dspi_sck to dspi_sout invalid ?2 ns ds7 dspi_sin to dspi_sck input setup 15 ns ds8 dspi_sck to dspi_sin input hold 0 ns 1. the delay is programmable in spix_ctarn[pssck] and spix_ctarn[cssck]. 2. the delay is programmable in spix_ctarn[pasc] and spix_ctarn[asc]. ds3 ds4 ds1 ds2 ds7 ds8 first data last data ds5 first data data last data ds6 data dspi_pcsn dspi_sck (cpol=0) dspi_sin dspi_sout figure 28. dspi classic spi timing master mode peripheral operating requirements and behaviors k60 sub-family data sheet data sheet, rev. 3, 2/2012. freescale semiconductor, inc. preliminary 63
table 44. slave mode dspi timing (limited voltage range) num description min. max. unit operating voltage 2.7 3.6 v frequency of operation 15 mhz ds9 dspi_sck input cycle time 4 x t bus ns ds10 dspi_sck input high/low time (t sck /2) ? 2 (t sck /2) + 2 ns ds11 dspi_sck to dspi_sout valid 10 ns ds12 dspi_sck to dspi_sout invalid 0 ns ds13 dspi_sin to dspi_sck input setup 2 ns ds14 dspi_sck to dspi_sin input hold 7 ns ds15 dspi_ss active to dspi_sout driven 14 ns ds16 dspi_ss inactive to dspi_sout not driven 14 ns first data last data first data data last data data ds15 ds10 ds9 ds16 ds11 ds12 ds14 ds13 dspi_ss dspi_sck (cpol=0) dspi_sout dspi_sin figure 29. dspi classic spi timing slave mode 6.8.8 dspi switching specifications (full voltage range) the dma serial peripheral interface (dspi) provides a synchronous serial bus with master and slave operations. many of the transfer attributes are programmable. the tables below provides dspi timing characteristics for classic spi timing modes. refer to the dspi chapter of the reference manual for information on the modified transfer formats used for communicating with slower peripheral devices. table 45. master mode dspi timing (full voltage range) num description min. max. unit notes operating voltage 1.71 3.6 v 1 frequency of operation 15 mhz table continues on the next page... peripheral operating requirements and behaviors k60 sub-family data sheet data sheet, rev. 3, 2/2012. 64 preliminary freescale semiconductor, inc.
table 45. master mode dspi timing (full voltage range) (continued) num description min. max. unit notes ds1 dspi_sck output cycle time 4 x t bus ns ds2 dspi_sck output high/low time (t sck /2) - 4 (t sck/2) + 4 ns ds3 dspi_pcs n valid to dspi_sck delay (t bus x 2) ? 4 ns 2 ds4 dspi_sck to dspi_pcs n invalid delay (t bus x 2) ? 4 ns 3 ds5 dspi_sck to dspi_sout valid 10 ns ds6 dspi_sck to dspi_sout invalid -4.5 ns ds7 dspi_sin to dspi_sck input setup 20.5 ns ds8 dspi_sck to dspi_sin input hold 0 ns 1. the dspi module can operate across the entire operating voltage for the processor, but to run across the full voltage range the maximum frequency of operation is reduced. 2. the delay is programmable in spix_ctarn[pssck] and spix_ctarn[cssck]. 3. the delay is programmable in spix_ctarn[pasc] and spix_ctarn[asc]. ds3 ds4 ds1 ds2 ds7 ds8 first data last data ds5 first data data last data ds6 data dspi_pcsn dspi_sck (cpol=0) dspi_sin dspi_sout figure 30. dspi classic spi timing master mode table 46. slave mode dspi timing (full voltage range) num description min. max. unit operating voltage 1.71 3.6 v frequency of operation 7.5 mhz ds9 dspi_sck input cycle time 8 x t bus ns ds10 dspi_sck input high/low time (t sck /2) - 4 (t sck/2) + 4 ns ds11 dspi_sck to dspi_sout valid 20 ns ds12 dspi_sck to dspi_sout invalid 0 ns ds13 dspi_sin to dspi_sck input setup 2 ns ds14 dspi_sck to dspi_sin input hold 7 ns ds15 dspi_ss active to dspi_sout driven 19 ns table continues on the next page... peripheral operating requirements and behaviors k60 sub-family data sheet data sheet, rev. 3, 2/2012. freescale semiconductor, inc. preliminary 65
table 46. slave mode dspi timing (full voltage range) (continued) num description min. max. unit ds16 dspi_ss inactive to dspi_sout not driven 19 ns first data last data first data data last data data ds15 ds10 ds9 ds16 ds11 ds12 ds14 ds13 dspi_ss dspi_sck (cpol=0) dspi_sout dspi_sin figure 31. dspi classic spi timing slave mode 6.8.9 i 2 c switching specifications see general switching specifications . 6.8.10 uart switching specifications see general switching specifications . 6.8.11 sdhc specifications the following timing specs are defined at the chip i/o pin and must be translated appropriately to arrive at timing specs/constraints for the physical interface. table 47. sdhc switching specifications num symbol description min. max. unit operating voltage 2.7 3.6 v card input clock table continues on the next page... peripheral operating requirements and behaviors k60 sub-family data sheet data sheet, rev. 3, 2/2012. 66 preliminary freescale semiconductor, inc.
table 47. sdhc switching specifications (continued) num symbol description min. max. unit sd1 fpp clock frequency (low speed) 0 400 khz fpp clock frequency (sd\sdio full speed) 0 25 mhz fpp clock frequency (mmc full speed) 0 20 mhz f od clock frequency (identification mode) 0 400 khz sd2 t wl clock low time 7 ns sd3 t wh clock high time 7 ns sd4 t tlh clock rise time 3 ns sd5 t thl clock fall time 3 ns sdhc output / card inputs sdhc_cmd, sdhc_dat (reference to sdhc_clk) sd6 t od sdhc output delay (output valid) -5 6.5 ns sdhc input / card inputs sdhc_cmd, sdhc_dat (reference to sdhc_clk) sd7 t isu sdhc input setup time 5 ns sd8 t ih sdhc input hold time 0 ns sd2sd3 sd1 sd6 sd8 sd7 sdhc_clk output sdhc_cmd output sdhc_dat[3:0] input sdhc_cmd input sdhc_dat[3:0] figure 32. sdhc timing 6.8.12 i2s/sai switching specifications this section provides the ac timing for the i2s/sai module in master mode (clocks are driven) and slave mode (clocks are input). all timing is given for noninverted serial clock polarity (tcr2[bcp] is 0, rcr2[bcp] is 0) and a noninverted frame sync (tcr4[fsp] peripheral operating requirements and behaviors k60 sub-family data sheet data sheet, rev. 3, 2/2012. freescale semiconductor, inc. preliminary 67
is 0, rcr4[fsp] is 0). if the polarity of the clock and/or the frame sync have been inverted, all the timing remains valid by inverting the bit clock signal (bclk) and/or the frame sync (fs) signal shown in the following figures. table 48. i2s/sai master mode timing num. characteristic min. max. unit operating voltage 1.71 3.6 v s1 i2s_mclk cycle time 1 40 ns s2 i2s_mclk pulse width high/low 45% 55% mclk period s3 i2s_tx_bclk cycle time (output) 1 i2s_rx_bclk cycle time (output) 1 80 160 ns s4 i2s_tx_bclk pulse width high/low 45% 55% bclk period s5 i2s_tx_bclk/i2s_rx_bclk to i2s_tx_fs/ i2s_rx_fs output valid 15 ns s6 i2s_tx_bclk/i2s_rx_bclk to i2s_tx_fs/ i2s_rx_fs output invalid 0 ns s7 i2s_tx_bclk to i2s_txd valid 15 ns s8 i2s_tx_bclk to i2s_txd invalid 0 ns s9 i2s_rxd/i2s_rx_fs input setup before i2s_rx_bclk 25 ns s10 i2s_rxd/i2s_rx_fs input hold after i2s_rx_bclk 0 ns s11 i2s_tx_fs input assertion to i2s_txd output valid 2 21 ns 1. this parameter is limited in vlpx modes. 2. applies to first bit in each frame and only if the tcr4[fse] bit is clear s1 s2 s2 s3 s4 s4 s5 s9 s7 s9 s10 s7 s8 s6 s10 s8 i2s_mclk (output) i2s_tx_bclk/ i2s_rx_bclk (output) i2s_tx_fs/ i2s_rx_fs (output) i2s_tx_fs/ i2s_rx_fs (input) i2s_txd i2s_rxd figure 33. i2s/sai timing master modes peripheral operating requirements and behaviors k60 sub-family data sheet data sheet, rev. 3, 2/2012. 68 preliminary freescale semiconductor, inc.
table 49. i2s/sai slave mode timing num. characteristic min. max. unit operating voltage 1.71 3.6 v s11 i2s_rx_bclk cycle time (input) i2s_tx_bclk cycle time (input) 80 160 ns s12 i2s_tx_bclk/i2s_rx_bclk pulse width high/low (input) 45% 55% mclk period s13 i2s_tx_fs/i2s_rx_fs input setup before i2s_tx_bclk/i2s_rx_bclk 10 ns s14 i2s_tx_fs/i2s_rx_fs input hold after i2s_tx_bclk/i2s_rx_bclk 2 ns s15 i2s_tx_bclk to i2s_txd/i2s_tx_fs output valid 29 ns s16 i2s_tx_bclk to i2s_txd/i2s_tx_fs output invalid 0 ns s17 i2s_rxd setup before i2s_rx_bclk 10 ns s18 i2s_rxd hold after i2s_rx_bclk 2 ns s19 i2s_tx_fs input assertion to i2s_txd output valid 1 21 ns 1. applies to first bit in each frame and only if the tcr4[fse] bit is clear s15 s13 s15 s17 s18 s15 s16 s16 s14 s16 s11 s12 s12 i2s_tx_bclk/ i2s_rx_bclk (input) i2s_tx_fs/ i2s_rx_fs (output) i2s_txd i2s_rxd i2s_tx_fs/ i2s_rx_fs (input) figure 34. i2s/sai timing slave modes 6.9 human-machine interfaces (hmi) peripheral operating requirements and behaviors k60 sub-family data sheet data sheet, rev. 3, 2/2012. freescale semiconductor, inc. preliminary 69
6.9.1 tsi electrical specifications table 50. tsi electrical specifications symbol description min. typ. max. unit notes v ddtsi operating voltage 1.71 3.6 v c ele target electrode capacitance range 1 20 500 pf 1 f refmax reference oscillator frequency 8 tbd mhz 2 f elemax electrode oscillator frequency 0.5 tbd mhz 2 c ref internal reference capacitor tbd 1 tbd pf v delta oscillator delta voltage tbd 600 tbd mv 2 i ref reference oscillator current source base current ? 1ua setting (refchrg=0) ? 32ua setting (refchrg=31) 1.133 36 1.5 50 a 2 , 3 i ele electrode oscillator current source base current ? 1ua setting (extchrg=0) ? 32ua setting (extchrg=31) 1.133 36 1.5 50 a 2 , 4 pres5 electrode capacitance measurement precision 8.3333 38.4 pf/count 5 pres20 electrode capacitance measurement precision 8.3333 38.4 pf/count 6 pres100 electrode capacitance measurement precision 8.3333 38.4 pf/count 7 maxsens maximum sensitivity 0.003 12.5 ff/count 8 res resolution 16 bits t con20 response time @ 20 pf 8 15 25 s 9 i tsi_run current added in run mode 55 a i tsi_lp low power mode current adder 1.3 tbd a 10 1. the tsi module is functional with capacitance values outside this range. however, optimal performance is not guaranteed. 2. fixed external capacitance of 20 pf. 3. the programmable current source value is generated by multiplying the scanc[refchrg] value and the base current. 4. the programmable current source value is generated by multiplying the scanc[extchrg] value and the base current. 5. measured with a 5 pf electrode, reference oscillator frequency of 10 mhz, ps = 128, nscn = 8; iext = 16. 6. measured with a 20 pf electrode, reference oscillator frequency of 10 mhz, ps = 128, nscn = 2; iext = 16. 7. measured with a 20 pf electrode, reference oscillator frequency of 10 mhz, ps = 16, nscn = 3; iext = 16. 8. sensitivity defines the minimum capacitance change when a single count from the tsi module changes, it is equal to (c ref * i ext )/( i ref * ps * nscn). sensitivity depends on the configuration used. the typical value listed is based on the following configuration: iext = 5 a, extchrg = 4, ps = 128, nscn = 2, i ref = 16 a, refchrg = 15, c ref = 1.0 pf. the minimum sensitivity describes the smallest possible capacitance that can be measured by a single count (this is the best sensitivity but is described as a minimum because its the smallest number). the minimum sensitivity parameter is based on the following configuration: i ext = 1 a, extchrg = 0, ps = 128, nscn = 32, i ref = 32 a, refchrg = 31, c ref = 0.5 pf 9. time to do one complete measurement of the electrode. sensitivity resolution of 0.0133 pf, ps = 0, nscn = 0, 1 electrode, extchrg = 15. 10. refchrg=0, extchrg=4, ps=7, nscn=0f, lpscnitv=f, lpo is selected (1 khz), and fixed external capacitance of 20 pf. data is captured with an average of 7 periods window. 7 dimensions dimensions k60 sub-family data sheet data sheet, rev. 3, 2/2012. 70 preliminary freescale semiconductor, inc.
7.1 obtaining package dimensions package dimensions are provided in package drawings. to find a package drawing, go to http://www.freescale.com and perform a keyword search for the drawings document number: if you want the drawing for this package then use this document number 144-pin lqfp 98ass23177w 144-pin mapbga 98asa00222d 8 pinout 8.1 k60 signal multiplexing and pin assignments the following table shows the signals available on each pin and the locations of these pins on the devices supported by this document. the port control module is responsible for selecting which alt functionality is available on each pin. 144 lqf p 144 map bga pin name default alt0 alt1 alt2 alt3 alt4 alt5 alt6 alt7 ezport l5 rtc_wake up_b rtc_wake up_b rtc_wake up_b m5 nc nc nc a10 nc nc nc b10 nc nc nc c10 nc nc nc 1 d3 pte0 adc1_se4 a adc1_se4 a pte0 spi1_pcs1 uart1_tx sdhc0_d1 i2c1_sda rtc_clko ut 2 d2 pte1/ llwu_p0 adc1_se5 a adc1_se5 a pte1/ llwu_p0 spi1_sout uart1_rx sdhc0_d0 i2c1_scl spi1_sin 3 d1 pte2/ llwu_p1 adc1_se6 a adc1_se6 a pte2/ llwu_p1 spi1_sck uart1_ct s_b sdhc0_dc lk 4 e4 pte3 adc1_se7 a adc1_se7 a pte3 spi1_sin uart1_rt s_b sdhc0_cm d spi1_sout 5 e5 vdd vdd vdd 6 f6 vss vss vss 7 e3 pte4/ llwu_p2 disabled pte4/ llwu_p2 spi1_pcs0 uart3_tx sdhc0_d3 8 e2 pte5 disabled pte5 spi1_pcs2 uart3_rx sdhc0_d2 ftm3_ch0 pinout k60 sub-family data sheet data sheet, rev. 3, 2/2012. freescale semiconductor, inc. preliminary 71
144 lqf p 144 map bga pin name default alt0 alt1 alt2 alt3 alt4 alt5 alt6 alt7 ezport 9 e1 pte6 disabled pte6 spi1_pcs3 uart3_ct s_b i2s0_mclk ftm3_ch1 usb_sof_ out 10 f4 pte7 disabled pte7 uart3_rt s_b i2s0_rxd0 ftm3_ch2 11 f3 pte8 adc2_se1 6 adc2_se1 6 pte8 i2s0_rxd1 uart5_tx i2s0_rx_f s ftm3_ch3 12 f2 pte9 adc2_se1 7 adc2_se1 7 pte9 i2s0_txd1 uart5_rx i2s0_rx_b clk ftm3_ch4 13 f1 pte10 disabled pte10 uart5_ct s_b i2s0_txd0 ftm3_ch5 14 g4 pte11 adc3_se1 6 adc3_se1 6 pte11 uart5_rt s_b i2s0_tx_f s ftm3_ch6 15 g3 pte12 adc3_se1 7 adc3_se1 7 pte12 i2s0_tx_b clk ftm3_ch7 16 e6 vdd vdd vdd 17 f7 vss vss vss 18 h3 vss vss vss 19 h1 usb0_dp usb0_dp usb0_dp 20 h2 usb0_dm usb0_dm usb0_dm 21 g1 vout33 vout33 vout33 22 g2 vregin vregin vregin 23 j1 pga2_dp/ adc2_dp0/ adc3_dp3/ adc0_dp1 pga2_dp/ adc2_dp0/ adc3_dp3/ adc0_dp1 pga2_dp/ adc2_dp0/ adc3_dp3/ adc0_dp1 24 j2 pga2_dm/ adc2_dm0/ adc3_dm3/ adc0_dm1 pga2_dm/ adc2_dm0/ adc3_dm3/ adc0_dm1 pga2_dm/ adc2_dm0/ adc3_dm3/ adc0_dm1 25 k1 pga3_dp/ adc3_dp0/ adc2_dp3/ adc1_dp1 pga3_dp/ adc3_dp0/ adc2_dp3/ adc1_dp1 pga3_dp/ adc3_dp0/ adc2_dp3/ adc1_dp1 26 k2 pga3_dm/ adc3_dm0/ adc2_dm3/ adc1_dm1 pga3_dm/ adc3_dm0/ adc2_dm3/ adc1_dm1 pga3_dm/ adc3_dm0/ adc2_dm3/ adc1_dm1 27 l1 pga0_dp/ adc0_dp0/ adc1_dp3 pga0_dp/ adc0_dp0/ adc1_dp3 pga0_dp/ adc0_dp0/ adc1_dp3 28 l2 pga0_dm/ adc0_dm0/ adc1_dm3 pga0_dm/ adc0_dm0/ adc1_dm3 pga0_dm/ adc0_dm0/ adc1_dm3 29 m1 pga1_dp/ adc1_dp0/ adc0_dp3 pga1_dp/ adc1_dp0/ adc0_dp3 pga1_dp/ adc1_dp0/ adc0_dp3 pinout k60 sub-family data sheet data sheet, rev. 3, 2/2012. 72 preliminary freescale semiconductor, inc.
144 lqf p 144 map bga pin name default alt0 alt1 alt2 alt3 alt4 alt5 alt6 alt7 ezport 30 m2 pga1_dm/ adc1_dm0/ adc0_dm3 pga1_dm/ adc1_dm0/ adc0_dm3 pga1_dm/ adc1_dm0/ adc0_dm3 31 h5 vdda vdda vdda 32 g5 vrefh vrefh vrefh 33 g6 vrefl vrefl vrefl 34 h6 vssa vssa vssa 35 k3 adc1_se1 6/ cmp2_in2/ adc0_se2 2 adc1_se1 6/ cmp2_in2/ adc0_se2 2 adc1_se1 6/ cmp2_in2/ adc0_se2 2 36 j3 adc0_se1 6/ cmp1_in2/ adc0_se2 1 adc0_se1 6/ cmp1_in2/ adc0_se2 1 adc0_se1 6/ cmp1_in2/ adc0_se2 1 37 m3 vref_out/ cmp1_in5/ cmp0_in5/ adc1_se1 8 vref_out/ cmp1_in5/ cmp0_in5/ adc1_se1 8 vref_out/ cmp1_in5/ cmp0_in5/ adc1_se1 8 38 l3 dac0_out/ cmp1_in3/ adc0_se2 3 dac0_out/ cmp1_in3/ adc0_se2 3 dac0_out/ cmp1_in3/ adc0_se2 3 39 l4 dac1_out/ cmp0_in4/ cmp2_in3/ adc1_se2 3 dac1_out/ cmp0_in4/ cmp2_in3/ adc1_se2 3 dac1_out/ cmp0_in4/ cmp2_in3/ adc1_se2 3 40 m7 xtal32 xtal32 xtal32 41 m6 extal32 extal32 extal32 42 l6 vbat vbat vbat 43 vdd vdd vdd 44 vss vss vss 45 m4 pte24 adc0_se1 7/extal1 adc0_se1 7/extal1 pte24 can1_tx uart4_tx i2s1_tx_f s ewm_out _b i2s1_rxd1 46 k5 pte25 adc0_se1 8/xtal1 adc0_se1 8/xtal1 pte25 can1_rx uart4_rx i2s1_tx_b clk ewm_in i2s1_txd1 47 k4 pte26 adc3_se5 b adc3_se5 b pte26 enet_1588 _clkin uart4_ct s_b i2s1_txd0 rtc_clko ut usb_clkin 48 j4 pte27 adc3_se4 b adc3_se4 b pte27 uart4_rt s_b i2s1_mclk 49 h4 pte28 adc3_se7 a adc3_se7 a pte28 50 j5 pta0 jtag_tcl k/ tsi0_ch1 pta0 uart0_ct s_b/ ftm0_ch5 jtag_tcl k/ swd_clk ezp_clk pinout k60 sub-family data sheet data sheet, rev. 3, 2/2012. freescale semiconductor, inc. preliminary 73
144 lqf p 144 map bga pin name default alt0 alt1 alt2 alt3 alt4 alt5 alt6 alt7 ezport swd_clk/ ezp_clk uart0_co l_b 51 j6 pta1 jtag_tdi/ ezp_di tsi0_ch2 pta1 uart0_rx ftm0_ch6 jtag_tdi ezp_di 52 k6 pta2 jtag_tdo/ trace_sw o/ezp_do tsi0_ch3 pta2 uart0_tx ftm0_ch7 jtag_tdo/ trace_sw o ezp_do 53 k7 pta3 jtag_tms/ swd_dio tsi0_ch4 pta3 uart0_rt s_b ftm0_ch0 jtag_tms/ swd_dio 54 l7 pta4/ llwu_p3 nmi_b/ ezp_cs_b tsi0_ch5 pta4/ llwu_p3 ftm0_ch1 nmi_b ezp_cs_b 55 m8 pta5 disabled pta5 usb_clkin ftm0_ch2 rmii0_rxe r/ mii0_rxer cmp2_out i2s0_tx_b clk jtag_trs t_b 56 e7 vdd vdd vdd 57 g7 vss vss vss 58 j7 pta6 adc3_se6 a adc3_se6 a pta6 ulpi_clk ftm0_ch3 i2s1_rxd0 clkout trace_cl kout 59 j8 pta7 adc0_se1 0 adc0_se1 0 pta7 ulpi_dir ftm0_ch4 i2s1_rx_b clk trace_d3 60 k8 pta8 adc0_se1 1 adc0_se1 1 pta8 ulpi_nxt ftm1_ch0 i2s1_rx_f s ftm1_qd_ pha trace_d2 61 l8 pta9 adc3_se5 a adc3_se5 a pta9 ulpi_stp ftm1_ch1 mii0_rxd3 ftm1_qd_ phb trace_d1 62 m9 pta10 adc3_se4 a adc3_se4 a pta10 ulpi_data 0 ftm2_ch0 mii0_rxd2 ftm2_qd_ pha trace_d0 63 l9 pta11 adc3_se1 5 adc3_se1 5 pta11 ulpi_data 1 ftm2_ch1 mii0_rxcl k ftm2_qd_ phb 64 k9 pta12 cmp2_in0 cmp2_in0 pta12 can0_tx ftm1_ch0 rmii0_rxd 1/ mii0_rxd1 i2s0_txd0 ftm1_qd_ pha 65 j9 pta13/ llwu_p4 cmp2_in1 cmp2_in1 pta13/ llwu_p4 can0_rx ftm1_ch1 rmii0_rxd 0/ mii0_rxd0 i2s0_tx_f s ftm1_qd_ phb 66 l10 pta14 cmp3_in0 cmp3_in0 pta14 spi0_pcs0 uart0_tx rmii0_crs _dv/ mii0_rxdv i2s0_rx_b clk i2s0_txd1 67 l11 pta15 cmp3_in1 cmp3_in1 pta15 spi0_sck uart0_rx rmii0_txe n/ mii0_txen i2s0_rxd0 68 k10 pta16 cmp3_in2 cmp3_in2 pta16 spi0_sout uart0_ct s_b/ uart0_co l_b rmii0_txd 0/ mii0_txd0 i2s0_rx_f s i2s0_rxd1 69 k11 pta17 adc1_se1 7 adc1_se1 7 pta17 spi0_sin uart0_rt s_b rmii0_txd 1/ mii0_txd1 i2s0_mclk 70 e8 vdd vdd vdd pinout k60 sub-family data sheet data sheet, rev. 3, 2/2012. 74 preliminary freescale semiconductor, inc.
144 lqf p 144 map bga pin name default alt0 alt1 alt2 alt3 alt4 alt5 alt6 alt7 ezport 71 g8 vss vss vss 72 m12 pta18 extal0 extal0 pta18 ftm0_flt2 ftm_clkin 0 73 m11 pta19 xtal0 xtal0 pta19 ftm1_flt0 ftm_clkin 1 lptmr0_a lt1 74 l12 reset_b reset_b reset_b 75 k12 pta24 cmp3_in4 cmp3_in4 pta24 ulpi_data 2 mii0_txd2 fb_a29 76 j12 pta25 cmp3_in5 cmp3_in5 pta25 ulpi_data 3 mii0_txcl k fb_a28 77 j11 pta26 adc2_se1 5 adc2_se1 5 pta26 ulpi_data 4 mii0_txd3 fb_a27 78 j10 pta27 adc2_se1 4 adc2_se1 4 pta27 ulpi_data 5 mii0_crs fb_a26 79 h12 pta28 adc2_se1 3 adc2_se1 3 pta28 ulpi_data 6 mii0_txer fb_a25 80 h11 pta29 adc2_se1 2 adc2_se1 2 pta29 ulpi_data 7 mii0_col fb_a24 81 h10 ptb0/ llwu_p5 adc0_se8/ adc1_se8/ adc2_se8/ adc3_se8/ tsi0_ch0 adc0_se8/ adc1_se8/ adc2_se8/ adc3_se8/ tsi0_ch0 ptb0/ llwu_p5 i2c0_scl ftm1_ch0 rmii0_mdi o/ mii0_mdio ftm1_qd_ pha 82 h9 ptb1 adc0_se9/ adc1_se9/ adc2_se9/ adc3_se9/ tsi0_ch6 adc0_se9/ adc1_se9/ adc2_se9/ adc3_se9/ tsi0_ch6 ptb1 i2c0_sda ftm1_ch1 rmii0_mdc /mii0_mdc ftm1_qd_ phb 83 g12 ptb2 adc0_se1 2/tsi0_ch7 adc0_se1 2/tsi0_ch7 ptb2 i2c0_scl uart0_rt s_b enet0_158 8_tmr0 ftm0_flt3 84 g11 ptb3 adc0_se1 3/tsi0_ch8 adc0_se1 3/tsi0_ch8 ptb3 i2c0_sda uart0_ct s_b/ uart0_co l_b enet0_158 8_tmr1 ftm0_flt0 85 g10 ptb4 adc1_se1 0 adc1_se1 0 ptb4 enet0_158 8_tmr2 ftm1_flt0 86 g9 ptb5 adc1_se1 1 adc1_se1 1 ptb5 enet0_158 8_tmr3 ftm2_flt0 87 f12 ptb6 adc1_se1 2 adc1_se1 2 ptb6 fb_ad23 88 f11 ptb7 adc1_se1 3 adc1_se1 3 ptb7 fb_ad22 89 f10 ptb8 disabled ptb8 uart3_rt s_b fb_ad21 90 f9 ptb9 disabled ptb9 spi1_pcs1 uart3_ct s_b fb_ad20 91 e12 ptb10 adc1_se1 4 adc1_se1 4 ptb10 spi1_pcs0 uart3_rx i2s1_tx_b clk fb_ad19 ftm0_flt1 pinout k60 sub-family data sheet data sheet, rev. 3, 2/2012. freescale semiconductor, inc. preliminary 75
144 lqf p 144 map bga pin name default alt0 alt1 alt2 alt3 alt4 alt5 alt6 alt7 ezport 92 e11 ptb11 adc1_se1 5 adc1_se1 5 ptb11 spi1_sck uart3_tx i2s1_tx_f s fb_ad18 ftm0_flt2 93 h7 vss vss vss 94 f5 vdd vdd vdd 95 e10 ptb16 tsi0_ch9 tsi0_ch9 ptb16 spi1_sout uart0_rx i2s1_txd0 fb_ad17 ewm_in 96 e9 ptb17 tsi0_ch10 tsi0_ch10 ptb17 spi1_sin uart0_tx i2s1_txd1 fb_ad16 ewm_out _b 97 d12 ptb18 tsi0_ch11 tsi0_ch11 ptb18 can0_tx ftm2_ch0 i2s0_tx_b clk fb_ad15 ftm2_qd_ pha 98 d11 ptb19 tsi0_ch12 tsi0_ch12 ptb19 can0_rx ftm2_ch1 i2s0_tx_f s fb_oe_b ftm2_qd_ phb 99 d10 ptb20 adc2_se4 a adc2_se4 a ptb20 spi2_pcs0 fb_ad31/ nfc_data 15 cmp0_out 100 d9 ptb21 adc2_se5 a adc2_se5 a ptb21 spi2_sck fb_ad30/ nfc_data 14 cmp1_out 101 c12 ptb22 disabled ptb22 spi2_sout fb_ad29/ nfc_data 13 cmp2_out 102 c11 ptb23 disabled ptb23 spi2_sin spi0_pcs5 fb_ad28/ nfc_data 12 cmp3_out 103 b12 ptc0 adc0_se1 4/ tsi0_ch13 adc0_se1 4/ tsi0_ch13 ptc0 spi0_pcs4 pdb0_ext rg fb_ad14/ nfc_data 11 i2s0_txd1 104 b11 ptc1/ llwu_p6 adc0_se1 5/ tsi0_ch14 adc0_se1 5/ tsi0_ch14 ptc1/ llwu_p6 spi0_pcs3 uart1_rt s_b ftm0_ch0 fb_ad13/ nfc_data 10 i2s0_txd0 105 a12 ptc2 adc0_se4 b/ cmp1_in0/ tsi0_ch15 adc0_se4 b/ cmp1_in0/ tsi0_ch15 ptc2 spi0_pcs2 uart1_ct s_b ftm0_ch1 fb_ad12/ nfc_data 9 i2s0_tx_f s 106 a11 ptc3/ llwu_p7 cmp1_in1 cmp1_in1 ptc3/ llwu_p7 spi0_pcs1 uart1_rx ftm0_ch2 clkout i2s0_tx_b clk 107 h8 vss vss vss 108 vdd vdd vdd 109 a9 ptc4/ llwu_p8 disabled ptc4/ llwu_p8 spi0_pcs0 uart1_tx ftm0_ch3 fb_ad11/ nfc_data 8 cmp1_out i2s1_tx_b clk 110 d8 ptc5/ llwu_p9 disabled ptc5/ llwu_p9 spi0_sck lptmr0_a lt2 i2s0_rxd0 fb_ad10/ nfc_data 7 cmp0_out i2s1_tx_f s 111 c8 ptc6/ llwu_p10 cmp0_in0 cmp0_in0 ptc6/ llwu_p10 spi0_sout pdb0_ext rg i2s0_rx_b clk fb_ad9/ nfc_data 6 i2s0_mclk pinout k60 sub-family data sheet data sheet, rev. 3, 2/2012. 76 preliminary freescale semiconductor, inc.
144 lqf p 144 map bga pin name default alt0 alt1 alt2 alt3 alt4 alt5 alt6 alt7 ezport 112 b8 ptc7 cmp0_in1 cmp0_in1 ptc7 spi0_sin usb_sof_ out i2s0_rx_f s fb_ad8/ nfc_data 5 113 a8 ptc8 adc1_se4 b/ cmp0_in2 adc1_se4 b/ cmp0_in2 ptc8 ftm3_ch4 i2s0_mclk fb_ad7/ nfc_data 4 114 d7 ptc9 adc1_se5 b/ cmp0_in3 adc1_se5 b/ cmp0_in3 ptc9 ftm3_ch5 i2s0_rx_b clk fb_ad6/ nfc_data 3 ftm2_flt0 115 c7 ptc10 adc1_se6 b adc1_se6 b ptc10 i2c1_scl ftm3_ch6 i2s0_rx_f s fb_ad5/ nfc_data 2 i2s1_mclk 116 b7 ptc11/ llwu_p11 adc1_se7 b adc1_se7 b ptc11/ llwu_p11 i2c1_sda ftm3_ch7 i2s0_rxd1 fb_rw_b/ nfc_we 117 a7 ptc12 disabled ptc12 uart4_rt s_b fb_ad27 ftm3_flt0 118 d6 ptc13 disabled ptc13 uart4_ct s_b fb_ad26 119 c6 ptc14 disabled ptc14 uart4_rx fb_ad25 120 b6 ptc15 disabled ptc15 uart4_tx fb_ad24 121 vss vss vss 122 vdd vdd vdd 123 a6 ptc16 disabled ptc16 can1_rx uart3_rx enet0_158 8_tmr0 fb_cs5_b/ fb_tsiz1/ fb_be23_1 6_b nfc_rb 124 d5 ptc17 disabled ptc17 can1_tx uart3_tx enet0_158 8_tmr1 fb_cs4_b/ fb_tsiz0/ fb_be31_2 4_b nfc_ce0_ b 125 c5 ptc18 disabled ptc18 uart3_rt s_b enet0_158 8_tmr2 fb_tbst_b /fb_cs2_b/ fb_be15_8 _b nfc_ce1_ b 126 b5 ptc19 disabled ptc19 uart3_ct s_b enet0_158 8_tmr3 fb_cs3_b/ fb_be7_0_ b fb_ta_b 127 a5 ptd0/ llwu_p12 disabled ptd0/ llwu_p12 spi0_pcs0 uart2_rt s_b ftm3_ch0 fb_ale/ fb_cs1_b/ fb_ts_b i2s1_rxd1 128 d4 ptd1 adc0_se5 b adc0_se5 b ptd1 spi0_sck uart2_ct s_b ftm3_ch1 fb_cs0_b i2s1_rxd0 129 c4 ptd2/ llwu_p13 disabled ptd2/ llwu_p13 spi0_sout uart2_rx ftm3_ch2 fb_ad4 i2s1_rx_f s 130 b4 ptd3 disabled ptd3 spi0_sin uart2_tx ftm3_ch3 fb_ad3 i2s1_rx_b clk 131 a4 ptd4/ llwu_p14 disabled ptd4/ llwu_p14 spi0_pcs1 uart0_rt s_b ftm0_ch4 fb_ad2/ nfc_data 1 ewm_in pinout k60 sub-family data sheet data sheet, rev. 3, 2/2012. freescale semiconductor, inc. preliminary 77
144 lqf p 144 map bga pin name default alt0 alt1 alt2 alt3 alt4 alt5 alt6 alt7 ezport 132 a3 ptd5 adc0_se6 b adc0_se6 b ptd5 spi0_pcs2 uart0_ct s_b/ uart0_co l_b ftm0_ch5 fb_ad1/ nfc_data 0 ewm_out _b 133 a2 ptd6/ llwu_p15 adc0_se7 b adc0_se7 b ptd6/ llwu_p15 spi0_pcs3 uart0_rx ftm0_ch6 fb_ad0 ftm0_flt0 134 m10 vss vss vss 135 f8 vdd vdd vdd 136 a1 ptd7 disabled ptd7 cmt_iro uart0_tx ftm0_ch7 ftm0_flt1 137 c9 ptd8 disabled ptd8 i2c0_scl uart5_rx fb_a16/ nfc_cle 138 b9 ptd9 disabled ptd9 i2c0_sda uart5_tx fb_a17/ nfc_ale 139 b3 ptd10 disabled ptd10 uart5_rt s_b fb_a18/ nfc_re 140 b2 ptd11 disabled ptd11 spi2_pcs0 uart5_ct s_b sdhc0_cl kin fb_a19 141 b1 ptd12 disabled ptd12 spi2_sck ftm3_flt0 sdhc0_d4 fb_a20 142 c3 ptd13 disabled ptd13 spi2_sout sdhc0_d5 fb_a21 143 c2 ptd14 disabled ptd14 spi2_sin sdhc0_d6 fb_a22 144 c1 ptd15 disabled ptd15 spi2_pcs1 sdhc0_d7 fb_a23 8.2 k60 pinouts the below figure shows the pinout diagram for the devices supported by this document. many signals may be multiplexed onto a single pin. to determine what signals can be used on which pin, see the previous section. pinout k60 sub-family data sheet data sheet, rev. 3, 2/2012. 78 preliminary freescale semiconductor, inc.
20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 75 74 73 60 59 58 57 56 55 54 53 52 51 72 71 70 69 68 67 66 65 64 63 62 61 25 24 23 22 21 40 39 38 37 50 49 48 47 46 45 44 43 42 41 36 35 34 33 32 31 30 29 28 27 26 99 79 78 77 76 98 97 96 95 94 93 92 91 90 89 88 80 81 82 83 84 85 86 87 100 108 vdd 107 106 105 104 103 102 101 vss ptc3/llwu_p7 ptc2 ptc1/llwu_p6 ptc0 ptb23 ptb22 116 ptc11/llwu_p11 115 114 113 112 111 110 109 ptc10 ptc9 ptc8 ptc7 ptc6/llwu_p10 ptc5/llwu_p9 ptc4/llwu_p8 124 ptc17 123 122 121 120 119 118 117 ptc16 vdd vss ptc15 ptc14 ptc13 ptc12 132 ptd5 131 130 129 128 127 126 125 ptd4/llwu_p14 ptd3 ptd2/llwu_p13 ptd1 ptd0/llwu_p12 ptc19 ptc18 140 ptd11 139 138 137 136 135 134 133 ptd10 ptd9 ptd8 ptd7 vdd vss ptd6/llwu_p15 144 143 142 141 ptd15 ptd14 ptd13 ptd12 ptb20 pta28 pta27 pta26 pta25 ptb19 ptb18 ptb17 ptb16 vdd vss ptb11 ptb10 ptb9 ptb8 ptb7 pta29 ptb0/llwu_p5 ptb1 ptb2 ptb3 ptb4 ptb5 ptb6 ptb21 pta24 reset_b pta19 pta18 vss vdd pta17 pta16 pta15 pta14 pta13/llwu_p4 pta12 pta11 pta10 pta9 pta8 pta7 pta6 vss vdd pta5 pta4/llwu_p3 pta3 pta2 pta1 pta0 pte28 pte27 pte26 pte25 pte24 vss vdd vbat extal32 xtal32 dac1_out/cmp0_in4/cmp2_in3/adc1_se23 dac0_out/cmp1_in3/adc0_se23 vref_out/cmp1_in5/cmp0_in5/adc1_se18 usb0_dm usb0_dp vss vss vdd pte12 pte11 pte10 pte9 pte8 pte7 pte6 pte5 pte4/llwu_p2 vss vdd pte3 pte2/llwu_p1 pte1/llwu_p0 pte0 pga3_dp/adc3_dp0/adc2_dp3/adc1_dp1 pga2_dm/adc2_dm0/adc3_dm3/adc0_dm1 pga2_dp/adc2_dp0/adc3_dp3/adc0_dp1 vregin vout33 adc0_se16/cmp1_in2/adc0_se21 adc1_se16/cmp2_in2/adc0_se22 vssa vrefl vrefh vdda pga1_dm/adc1_dm0/adc0_dm3 pga1_dp/adc1_dp0/adc0_dp3 pga0_dm/adc0_dm0/adc1_dm3 pga0_dp/adc0_dp0/adc1_dp3 pga3_dm/adc3_dm0/adc2_dm3/adc1_dm1 figure 35. k60 144 lqfp pinout diagram pinout k60 sub-family data sheet data sheet, rev. 3, 2/2012. freescale semiconductor, inc. preliminary 79
1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 a b c d e f g h j a b c d e f g h j 10 k k 10 11 11 l l 12 12 m m pta18 ptc8 llwu_p8 nc llwu_p7 ptc2 pta1 pta6pta0pte27 adc0_se16/ adc1_se16/ pte26 pte25 pta2 pta3 pta8 pta7 vssvssvssavddapte28vssusb0_dm pga2_dm/ pga3_dm/ pga0_dm/ dac0_out/ dac1_out/ wakeup_b vbat llwu_p3 pta9 pta11 pta12 llwu_p4 ptb1 pta27 llwu_p5 ptb4ptb5vssvssvreflvrefhpte11pte12vreginvout33 usb0_dp pga2_dp/ pga3_dp/ pga0_dp/ pga1_dp/ pga1_dm/ vref_out/ pte24 nc extal32 xtal32 pta5 pta10 vss pta16 pta14 ptb3 pta29 pta26 pta17 pta15 pta19 reset_b pta24 pta25 pta28 ptb2 ptb6ptb7ptb8ptb9vdd vdd ptb17 ptb16 ptb10ptb11 ptb19 ptb18 ptb22ptb23nc ptb20ptb21 llwu_p9 ptd8 llwu_p10 ptc7 ptd9 nc llwu_p6 ptc0 vss vss vddvdd ptc13 ptc9 llwu_p11 ptc10 ptc19 ptc15 ptc14ptc18 llwu_p13 ptd3ptd10 ptd13 pte0 ptd1 ptc17 vdd vddpte7 pte3 llwu_p2 pte8pte9pte10 pte6 pte5 llwu_p0llwu_p1 ptd15 ptd14 ptd11ptd12 ptc12ptc16 llwu_p12llwu_p14 ptd5 llwu_p15 ptd7 adc1_dp0/ adc0_dp3 adc1_dm0/ adc0_dm3 cmp1_in5/ cmp0_in5/ adc1_se18 pta4/ adc0_dp0/ adc1_dp3 adc0_dm0/ adc1_dm3 cmp1_in3/ adc0_se23 cmp0_in4/ cmp2_in3/ adc1_se23 rtc_ adc2_dp3/ adc1_dp1 adc3_dm0/ adc2_dm3/ adc1_dm1 cmp2_in2/ adc0_se22 pta13/ adc2_dp0/ adc3_dp3/ adc0_dp1 adc2_dm0/ adc3_dm3/ adc0_dm1 cmp1_in2/ adc0_se21 ptb0/ pte4/ pte2/ pte1/ ptc5/ ptc6/ptd2/ ptc11/ ptc1/ ptc3/ptc4/ ptd0/ptd4/ptd6/ figure 36. k60 144 mapbga pinout diagram 9 revision history the following table provides a revision history for this document. table 51. revision history rev. no. date substantial changes 1 6/2011 initial public revision. corrected usb conditions. table continues on the next page... revision history k60 sub-family data sheet data sheet, rev. 3, 2/2012. 80 preliminary freescale semiconductor, inc.
table 51. revision history (continued) rev. no. date substantial changes 2 11/2011 ? added ac electrical specifications. ? updated part identification section for 120 mhz cpu frequency. ? updated voltage and current operating ratings section. ? updated voltage and current operating requirements section. ? updated lvd and por operating requirements section. ? updated voltage and current operating behaviors section. ? updated power mode transition operating behaviors section. ? updated power consumption operating behaviors section. ? in run mode supply current vs. core frequency section, added run and vlpr modes supply current vs. core frequency diagrams. ? in device clock specifications section, updated flash clock frequency and ddr clock frequency. ? updated thermal attributes. ? in mcg specifications section, updated total deviation of trimmed average dco output frequency, pll reference frequency range, and lock detector detection time. ? in oscillator frequency specifications section, updated crystal startup time 32 khz. ? updated nfc specifications section. ? in dspi switching specifications section, updated master and slave modes frequency of operation for limited voltage and full voltage ranges. ? in i2s/sai switching specifications section, updated cycle time for master and slave modes. ? in usb dcd electrical specifications section, updated data detect voltage. ? in tsi electrical specifications, updated reference oscillator frequency. ? updated pinouts. ? updated pinouts. revision history k60 sub-family data sheet data sheet, rev. 3, 2/2012. freescale semiconductor, inc. preliminary 81
how to reach us: home page: www.freescale.com web support: http://www.freescale.com/support usa/europe or locations not listed: freescale semiconductor technical information center, el516 2100 east elliot road tempe, arizona 85284 +1-800-521-6274 or +1-480-768-2130 www.freescale.com/support europe, middle east, and africa: freescale halbleiter deutschland gmbh technical information center schatzbogen 7 81829 muenchen, germany +44 1296 380 456 (english) +46 8 52200080 (english) +49 89 92103 559 (german) +33 1 69 35 48 48 (french) www.freescale.com/support japan: freescale semiconductor japan ltd. headquarters arco tower 15f 1-8-1, shimo-meguro, meguro-ku, tokyo 153-0064 japan 0120 191014 or +81 3 5437 9125 support.japan@freescale.com asia/pacific: freescale semiconductor china ltd. exchange building 23f no. 118 jianguo road chaoyang district beijing 100022 china +86 10 5879 8000 support.asia@freescale.com document number: k60p144m120sf3 rev. 3, 2/2012 preliminary information in this document is provided solely to enable system and software implementers to use freescale semiconductors products. there are no express or implied copyright licenses granted hereunder to design or fabricate any integrated circuits or integrated circuits based on the information in this document. freescale semiconductor reserves the right to make changes without further notice to any products herein. freescale semiconductor makes no warranty, representation, or guarantee regarding the suitability of its products for any particular purpose, nor does freescale semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any liability, including without limitation consequential or incidental damages. "typical" parameters that may be provided in freescale semiconductor data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. all operating parameters, including "typicals", must be validated for each customer application by customer's technical experts. freescale semiconductor does not convey any license under its patent rights nor the rights of others. freescale semiconductor products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which failure of the freescale semiconductor product could create a situation where personal injury or death may occur. should buyer purchase or use freescale semiconductor products for any such unintended or unauthorized application, buyer shall indemnify freescale semiconductor and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claims alleges that freescale semiconductor was negligent regarding the design or manufacture of the part. rohs-compliant and/or pb-free versions of freescale products have the functionality and electrical characteristics as their non-rohs-complaint and/or non-pb-free counterparts. for further information, see http://www.freescale.com or contact your freescale sales representative. for information on freescale's environmental products program, go to http://www.freescale.com/epp. freescale? and the freescale logo are trademarks of freescale semiconductor, inc. all other product or service names are the property of their respective owners. ? 2012 freescale semiconductor, inc.

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